Arm vs RISC V- What You Need to Know

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Gary Explains

Gary Explains

День тому

Arm is a RISC Instruction Set Architecture (ISA) and simultaneously a company that designs RISC CPU cores. RISC-V is also a RISC ISA, but not also a design company. Are there any other differences? Let's find out.
TImecodes
00:00 Intro
00:58 History of Arm
04:02 Armv9
07:57 History of RISC-V
13:32 Differences
19:40 Future
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КОМЕНТАРІ: 612
@youcantata
@youcantata 2 роки тому
I'd like to see more technical explanation on architectural difference between the two RISC architectures like register model, branch model, addressing mode, data/cache management, memory management, priority, interrupt, privilege, security model, vector mode etc. This video is just business introduction of two.
@THB192
@THB192 2 роки тому
There's not really as much to say there. AArch64 has some weird instructions RV64 doesn't, and some design differences, but it's not that crazy. RV32 vs 32-bit ARM is a bit more exciting because 32-bit ARM is extremely quirky.
@reiniertl
@reiniertl 2 роки тому
Well you have all the specifications out there. Is hard stuff to digest but cool if yo really like to understand computer architecture.
@gast128
@gast128 2 роки тому
Agree. I wonder how much the differences in ISA would contribute to differences in performance. Even the ancient x86 CISC instruction set has been accelerated under the hood by Intel's and AMD's trickery.
@THB192
@THB192 2 роки тому
@@gast128 The answer to that question is "it's complicated". Chris Celio did a talk on this while he was working in the BOOM RISC-V out of order core. Sort of on this, really. It was about stacking up ISAs and comparing them. Thing is, the ISA can impact how many instructions your program is, but it can't determine how fast they run. That's the province of the microarchitecture and the process. And if there is one thing x86 has proven it's that you can make almost any ISA run fast. However, an ISA can make a microarchitect's job easy or hard. x86 makes the microarchitect's job much much harder than it needs to be, and not really to any gain for programs: it's just that every x86 CPU needs to implement 50 years of legacy. RISC-V makes the microarchitect's job much easier, and the chip real estate you don't have to use on making x86 not terrible can be utilized in other ways. Of course, Intel and AMD still have some of the best microarchitects in the world, exceptional fab technology at their disposal, and enough guaranteed customers to bankroll the design, testing, and production of chips (and the upfront cost of producing chips, especially on the very small processes that Intel and AMD are using, is very high). That's why x86 is still beating everyone else's performance. Of course, none of this actually matters if your compiler sucks at utilizing your ISA, or you blow your instruction or data cache, or any number of other things. It turns out even if your program is CPU-bound the microarchitecture isn't always the bottleneck. My credentials on this subject are... zero. I don't have any. Don't trust me.
@godnyx117
@godnyx117 2 роки тому
@@THB192 More quirky than X86_X64?
@JB52520
@JB52520 2 роки тому
The whole point of RISC-V is that you _can_ make open source hardware using the RISC-V ISA without getting sued out of existence, not that you must, or that the processors don't cost money. The designs may be open and their users may have freedom. It enables open collaboration, reuse, and expansion within a well-defined instruction space designed to prevent collisions between predefined and custom extension sets. There could be a whole ecosystem of open designs just for pieces of cores, or software cores, FPGA cores, free implementations of custom extensions, or whatever people want to create and share. It's very much like Linux for hardware.
@wertigon
@wertigon 2 роки тому
Indeed - while Gary is correct that someone still must build these designs, and building it especially large scale costs a lot of money, this cost can be greatly reduced by IP reuse. Software isn't exactly cheap to make either. Every CPU still needs an I/O die, and this is no different from every other I/O die on the market. Every CPU still needs a cache memory, FPU, and so on. These have existed for years, expired patents tell us how to build these already and as efficiently as possible. 90% of a CPU chip is the same components, so if these 90% were in the same standardized modular package that will eventually allow for lower costs. Think chiplets but at chip level. Think a CPU but sacrifice FPUs for hardware-accelerated packet switching. And so on. Lots of fun stuff that could be done here. :)
@DragonsinGenesisPodcast
@DragonsinGenesisPodcast 2 роки тому
Companies that design cores still patent those designs. While the architecture is open like Linux, the core designs and innovations that make those cores more useful and efficient can still be patented. And since the architecture is open, this will likely lead to multiple companies designing multiple cores using a variety of source codes that are controlled by different companies. This means that a unique innovation that could benefit all RISC V chips will only be available to whichever company designed it. So if one company designed a more efficient source code and another company designs a more powerful core, you can’t get a RISC V system that uses both the powerful core and efficient code because they’re property of two competing companies. This will lead to a fracturing of the technology with no single controlling all the best technologies. Instead the best innovations will be scattered among multiple designs, preventing any of them from reaching peak performance. This is not a limitation of ARM who can implement all innovations. This is why Intel is trying to buy up RISC V engineering companies, so they can control the best designs of these chips.
@laharl2k
@laharl2k 2 роки тому
if they would make an atmega pin compatible risc-V with faster speed and more memory it could really beat atmel on the arduino space in a second because even if its slow and obsolete many are still using it because thats what the arduinos come with and thats the platform the software was made on. It would be just a matter of making the chip and adding it to the arduino libraries. Just give me 300mhz and 4mb of ram and im sold.
@devdylan6152
@devdylan6152 2 роки тому
@@laharl2k the new ESP32 C3 is using RISC-V
@laharl2k
@laharl2k 2 роки тому
@@devdylan6152 Make that into an arduino uno and arduino mega form factor and it will sell, otherwise we are still in the same situation where everything people use ws made for those so they keep using those instead, even if there are better alternatives.
@thomasruwart1722
@thomasruwart1722 2 роки тому
I remember having the CISC vs RISC discussions in 1984 when I worked for a startup that was implementing a CPU using 6000-gate array logic from Control Data Corporation. We ended up implementing the MC68020 CISC instruction set in said gate arrays and it ran 10x the speed of the fastest 68020 chip at the time. But, as many startups of its time, it died in 2006 due to severe mismanagement at the top. Oh well, it was fun while it lasted.
@spguy7559
@spguy7559 2 роки тому
WoW . i'm from iran sir , is there any opportunity to understand RISC-V arch for me ? you swimming on the technology :) , if that's impossible we will find out the way from scratch . a nation under sanction can do anything finally .
@derrheat154
@derrheat154 Рік тому
@@spguy7559 Hi, there is an online course from UC Berkeley called CS61C. They teach RISC-V but I dont know why you would need to learn it.
@AnnatarTheMaia
@AnnatarTheMaia Рік тому
I'm going through teaching myself how to design circuits with the eventual goal of implementing my own MC68060-compatible core, not in design, but at an instruction level. Then after that, I'm going for synthesizing OpenSPARC T2 on an FPGA, with an eventual goal of building an OpenSPARC T2 1U 19" rack server. And then get the missing illumos support back in, which shouldn't be too difficult considering it comes from the SPARC platform. And then get SmartOS to build on it, once illumos support is upstreamed.
@thomasruwart1722
@thomasruwart1722 Рік тому
@@AnnatarTheMaia - That sounds like a fun project!
@AnnatarTheMaia
@AnnatarTheMaia Рік тому
@@thomasruwart1722 I'm having so much fun learning how to design electronic circuits, I completely "found myself" in it.
@fuseteam
@fuseteam 2 роки тому
if you add 00:00 intro to your timecodes youtube will segment the video in chapters :3
@randallcromer66
@randallcromer66 2 роки тому
I've always wanted to know the difference between the two and now I know. Thank you for sharing this cool information and video with us. You're really are one of the best UKposts channel's on here for everything about technology and for that I very much appreciate all you do to inform and educate us in this never ending change in technology. So please keep up the awesome work and I promise to keep coming back for more and sharing your video's with as many people as I possibly can because you definitely deserve it. 🤟🤓👍
@paco3447
@paco3447 2 роки тому
One important thing to note is that ARM Vector extensions are actually SIMD (single instruction multiple data) despite the name, and RISC-V is not SIMD but real vector instructions by design (like old Cray-1 style vectorial machines).
@gcm4312
@gcm4312 2 роки тому
big deal for A.I.
@BruceHoult
@BruceHoult 2 роки тому
ARM SVE is very similar to RISC-V V extension. Both are designed to deal with user vectors of any length (up to millions or billions of elements) using CPUs with vector registers of varying length (128 to 4096 bits for SVE, 32 to 2^32 bits for RISC-V) using exactly the same binary program instructions to give optimal results on any machine.
@paco3447
@paco3447 2 роки тому
@@BruceHoult Sorry, but not at all. RISC-V RVV vector extensions when contrasted with ARM SVEx follows a profoundly different strategy. Another problem with ARM vs RV is that the former is simply large (+1000 vs a mere 48 ins in RV), RVV vector instr. fit on one single page and have a pretty simple syntax (ex. a simple vector load ins: VLD v0, x10). Yep, length is pretty similar, but ARM FP registers overlaps in the same register file/memory. RVV does not work like ARM, as long as holds in a separate register file, for example. ARM vector complexity is above RVV. And so on
@BruceHoult
@BruceHoult 2 роки тому
@@paco3447 complexity is not a good thing in itself. Usability and effectiveness are just as important. I've been using real, production, RISC-V vector hardware (Alibaba C906 core) for several months now and it's very nice -- older 0.7.1 spec, but the differences between that and 1.0rc1 are trivial compared to the differences to SVE, let alone anything else.
@paco3447
@paco3447 2 роки тому
@@BruceHoult Yep. But you now that both follows different strategies in many aspects of V instructions. For example, dealing with variable length vectors (more simpler in favour of RISC-V). Or vector register file partitioning. Yes, both have same amount of vect. regist. but R-V allows disable those regs and give it back to memory. Differences when calculating max vector length, etc. I'm not saying ARM is bad but both have quite different approaches and personally I believe RISC-V is more simpler than ARM.
@gsQartman
@gsQartman 2 роки тому
Great overview - as always, thank you for quality content!
@soraaoixxthebluesky
@soraaoixxthebluesky 2 роки тому
We argue about ARM vs RISC-V. Now Prof gives us a new knowledge for us to learn. Lets go.
@esra_erimez
@esra_erimez 2 роки тому
This is the best treatment on the subject and its importance can't be over stated.
@nufosmatic
@nufosmatic 2 роки тому
From a compiler developer colleague - "RISC" stands for Real Important Stuff in Compilers...
@mytechnotalent
@mytechnotalent 2 роки тому
Brilliant as always Gary the most through comparison! Cheers!
@nufosmatic
@nufosmatic 2 роки тому
08:27 - I worked for a company that built a superminicomputer starting in about 1978 - Datacraft Slash 4 - 24 bits (twice as good as a PDP-8) 60us memory access - the 6024 architecture - and a memory-oriented RISC architecture with infinite indexing and hardware virtual memory. The good, old days of Silicon Beach aka Pompano Beach, Florida...
@jackmcmorrow
@jackmcmorrow 2 роки тому
Finally a clear comparison, I enjoyed it a lot!
@JOGEZAI
@JOGEZAI 2 роки тому
i am so glad that youtube suggested your channel❤
@daniahmed
@daniahmed 2 роки тому
The professor has graced us again with some quality content.
@mayurshah008
@mayurshah008 2 роки тому
Great one!!! Your videos are too much informative which no one else probably explain in the way you do it
@GaryExplains
@GaryExplains 2 роки тому
I appreciate that!
@primorock8141
@primorock8141 2 роки тому
I like the way you explain everything, you've gained a new subscriber!
@abdullahmubarak6840
@abdullahmubarak6840 2 роки тому
Thanks for the explanation Gary! Appreciate it.
@GegoXaren
@GegoXaren 2 роки тому
You forgot that EuroHPC is going to switch their cores from ARM to RISC-V for future designs. The compute module that they have designed are already RISC-V, but uses a an ARM cpu as an interface.
@OmDahake
@OmDahake 2 роки тому
waiting for this kind for a long long time, finally found this, still not exactly what I wanted but still a good one
@anythingbutASIC
@anythingbutASIC Рік тому
Gary explained a lot actually..
@TheJacklwilliams
@TheJacklwilliams 2 роки тому
Got my subscription. Dude you are, wild. THANK YOU. GREAT PRESENTATION!
@jonathangerard745
@jonathangerard745 2 роки тому
Was eagerly waiting for this video
@jimgolab536
@jimgolab536 2 роки тому
Very well explained. Your point about the danger of an MMX effect is very apt and very concerning, especially as 1) it is intrinsic to RISC-V and 2) explicitly avoided by ARM (If I understood correctly).
@Gruggo
@Gruggo 2 роки тому
After watching your video about Intel looking at RISC-V, I wanted to know how it differs to ARM but didn't find any vids or articles that outlined this specifically. And then this video shows up, thanks
@swarupkumar2
@swarupkumar2 2 роки тому
Exactly the video I was looking for
@melgross
@melgross 2 роки тому
So, I read somewhere that Armv9 is to a large extent a back port of Apple’s additions to the current v8, with whatever ARM may have added and modified. Apple went to 64 bits only way back with the A7, they’re coming up on the A15 a bit later this year.
@SchoolforHackers
@SchoolforHackers 2 роки тому
Prof. Gary keeps me in endless school.
@FlorinArjocu
@FlorinArjocu 2 роки тому
I am curious if the energy efficiency is similar between the RISC-V and the ARM one from a few years ago, the ones they said are comparable.
@davidhart1674
@davidhart1674 2 роки тому
Excellent explainer video! Gary I wonder if you can investigate and explain Apple's reportedly undocumented ARMv8 ISA extensions on the Apple M1 processor used to speed up x86 emulation.
@destrierofdark_
@destrierofdark_ 2 роки тому
They implement the Intel memory model as a massive performance hack.
@Bless3757
@Bless3757 2 роки тому
yessss i'd love a video on this
@davidhart1674
@davidhart1674 2 роки тому
@@destrierofdark_ does this mean that the Intel memory model when used executing x86-64 code works concurrently with the ARM load/store model when executing AArch64 code? Seems like a pretty sweet hack if they managed to do it with minimal silicon.
@destrierofdark_
@destrierofdark_ 2 роки тому
@@davidhart1674 I'd imagine some very specific ASIC to convert it, or whatever the load/store of the ARM is doing is adapted to Intel. Either approach works, and the hack obviously performs amazing, and considering it's still that low of a wattage on the M1, that should tell you something.
@mrjean9376
@mrjean9376 Рік тому
I'm in love reading all of this technical discussion, thank you very much guys
@worldhello1234
@worldhello1234 2 роки тому
@20:12 Yes, the Pinecil soldering iron from Pine64 features a RISC-V bumblebee microcontroller and is much more affordable than similar offerings with ARM microcontroller.
@GaryExplains
@GaryExplains 2 роки тому
I think I said popular and prevalent.
@tookitogo
@tookitogo Рік тому
As if the MCU were responsible for the price difference! 🤣
@michaelm1
@michaelm1 2 роки тому
What about OpenPOWER? Isn't that RISC too? And "open"? With good performance? Though insane price.
@BruceHoult
@BruceHoult 2 роки тому
"Still waiting for a popular, prevalent RISC-V Arduino rival". Well, "popular" is up to buyers, but there are a large number of RISC-V boards in the Arduino space and have been for several years: 1) FE-310 based boards such as the HiFive1, HiFive1 rev b, LoFive R1, SparkFun RED-V RedBoard, SparkFun RED-V Thing Plus, 2) GD32VF103 boards such as the $4.90 Longan Nano, 3) K210 boards from $12.90 MAix BiT and $21 Maixduino. The K210 chip offers dual core 64 bit running at 400 MHz with 8 MB SRAM, plus a lot of peripherals such as ML accelerators. Really great value.
@GaryExplains
@GaryExplains 2 роки тому
Popular is indeed up to the buyers that is the whole point. 🤦‍♂️
@vslow4795
@vslow4795 2 роки тому
Great video! I was delusional at multiple points, clarified for me!
@ThomasGodart
@ThomasGodart 2 роки тому
This video is pure gold. Thank you for sharing it 🙏
@rloadah
@rloadah Рік тому
Great observation on the difference between open source software and open source hardware!
@GaryExplains
@GaryExplains Рік тому
Glad it was helpful!
@shadow7037932
@shadow7037932 2 роки тому
I think RISC will basically replace ARM for smaller MCUs/ARM cores like M0 as the extensions will allow someone like Ti to tailor and optimize their MCUs for very specific applications.
@kibels894
@kibels894 Рік тому
ESP32-C3 is out now and it's great, think you will see a plenty of Arduino-like designs based on it!
@AwsAlSamarrie
@AwsAlSamarrie 2 роки тому
Thank you for this video
@dawienel1142
@dawienel1142 2 роки тому
You desearve more views, great content piece.
@galdutro
@galdutro 2 роки тому
I have an impression that the RISC-V revolution is more akin to ANSI C than it is to Linux.
@BruceHoult
@BruceHoult 2 роки тому
I'm thinking RISC-V is more like POSIX or the Single Unix Specification or something like that. Linux is just one "manufacturer" following this standard, with also the various *BSDs, Darwin, Windows with the appropriate subsystem, all the proprietary versions from Sun, HP, SGI etc. A mix of closed commercial and open source versions.
@paulperkins1615
@paulperkins1615 2 роки тому
@@BruceHoult If RISC-V is like POSIX, it is doomed to irrelevance. POSIX compliance looks like compatibility on paper, but that's all it's "good" for. To me it seems like an ISA is a language in which software is written, much as C is. An operating system is a different kind of beast.
@richardokeefe7410
@richardokeefe7410 2 роки тому
The BeagleV is now the VisionFive. Looking at the specs, and comparing it with the RPi 400 (which I have) drives home the fact that the ISA is not as important as it was. What counts is what is in the System-on-Chip. Graphics, vision processing, sound processing, neural net execution, deep learning, the CPU is only marginally involved in these. For many IoT applications, it's what the SoC offers here that will matter, not whether the CPU is ARM, x86, RISCV, or MIPS. RISCV enables *CPU* architecture research in a wonderful way. By the way, my RPi 400 came with the recommended power supply, but it doesn't have enough power on its USB ports to power any of the optical mice I have. I had to buy an extra powered USB hub.
@ichoudhury007
@ichoudhury007 2 роки тому
Excellent video
@zetaconvex1987
@zetaconvex1987 2 роки тому
Interesting overview. Thanks.
@GaryExplains
@GaryExplains 2 роки тому
My pleasure!
@berndeckenfels
@berndeckenfels 2 роки тому
Would be interesting to talk about european sovereignty plans in relation to RISC-V, if that helps here (also supply chain risks involved with the IP)
@F3ARNO3VIL
@F3ARNO3VIL 2 роки тому
I believe Si-Five Announced they're on P650 which is on the level of ARM Cortex-A77. Not bad IMO
@GaryExplains
@GaryExplains 2 роки тому
Still 3 years behind. And it isn't in any actual products.
@abriotde
@abriotde 2 роки тому
What is fun is that 10 years ago, you could say the same about ARM and X86 (ARM could only run on Linux and Android) and maybe 20 years ago it was just on special embeded devices. And now ARM is on servers and at least Intel may died (we don't know of course). The change can be quick and with a free ISA and state who have politic interest to look for non-USA product it can be ever quicker.
@TurboGoth
@TurboGoth 2 роки тому
OMG THANK YOU for mentioning the BeagleV! I didn't know about it! But I've marked my calendar for next September! I can't wait!!! I already have a Beaglebone and having a RISC-V machine running Linux will be some real fun! I wonder if the mainstream WASM runners will implement machine translation for that architecture by then. I bet not!
@GaryExplains
@GaryExplains 2 роки тому
It got cancelled.
@TurboGoth
@TurboGoth 2 роки тому
Oh no!!! I'm rubbing all lamps looking for a genie to wish on now.
@TurboGoth
@TurboGoth 2 роки тому
Furthermore, I've resolved to pull together some QEMU magic to get SOME OS running locally on RISC-V even if that OS is some minimal screen text loop. Oh hey! It looks like Debian has been ported to RISC-V. Here's hoping it can do with entirely virtualized devices. It might involve some annoying games but now i'm determined.
@GaryExplains
@GaryExplains 2 роки тому
I have a video about emulating RISC-V on a Pi using qemu.
@michaelrichter9427
@michaelrichter9427 2 роки тому
ARM chips are also found in a myriad of embedded systems, going the other direction.
@el-domo
@el-domo 2 роки тому
let me clearify something, for the ones who don't know about it: It is software in term of being a code, but it is not programming code. It is a description code (VHDL or Verilog) and when you write it you are not programming. You take this code and convert it do circuit and then to layout to make the hardware, or you use a FPGA as an example and "programm the hardware using the description code".
@mayurshah008
@mayurshah008 2 роки тому
If Intel is also moving to risc-v(considering sifive acquisition) does this means to end of cisc as well? Considering the result provided by risc based processors
@GaryExplains
@GaryExplains 2 роки тому
No, because if Intel does buy its way into RISC-V it will still keep developing and selling x86. Intel will likely use a business strategy that means that their RISC-V and x86 businesses won't overlap.
@nothing9220
@nothing9220 2 роки тому
In future... It will
@Athiril
@Athiril Рік тому
The ESP32-C3 is RISC-V iirc. I’d say that would be an Arduino alternative
@mark_5588
@mark_5588 2 роки тому
In a future video would you consider commenting on the likelihood of any of these being offered retail and gaining motherboard support to become a 3rd choice in the home computer DIY to compete against the current Intel and AMD offerings? What about a chip and board combo like the RPi and others with Linux performance rivaling the current generation for people who don't game and therefore do not need to support massive and expensive GPUs?
@jann5s___
@jann5s___ 2 роки тому
With all the current instruction features in armv9, can you still call it RISC?
@tookitogo
@tookitogo Рік тому
Indeed. In powerful processors, the RISC/CISC divide is really largely nonexistent, as RISC processors gained many more instructions, and CISC processors started breaking down “complex” instructions into simpler ones under the hood before sending them for execution.
@madmotorcyclist
@madmotorcyclist 2 роки тому
You should do a youtube about LISP machines that were used to usher AI in during the 1980s-90s. It's sad such a powerful language didn't catch on.
@candyemrys564
@candyemrys564 2 роки тому
I agree. I still use lisp. I like legacy systems.
@murraymadness4674
@murraymadness4674 2 роки тому
As one of three authors of multiple process lisp systems, I ported to 4 different multiple cpu machines, that cost $100,000+, and now a $5 PI has two, and $10 chips have 4, and we still can't program them effectively in parallel after 30 years. I am so tempted to bring back my NICL system, yet nobody would care.
@madmotorcyclist
@madmotorcyclist 2 роки тому
@@murraymadness4674 I hear you. I did my initial work on Symbolics machines and finally ported over to Allegro Lisp on Sparcs.
@AZOffRoadster
@AZOffRoadster 2 роки тому
@@madmotorcyclist At my last job we had Sparc Stations everywhere. My favorite part? The bios written in Forth.
@pmarreck
@pmarreck 2 роки тому
I remember visiting my CS212 prof for office hours in the early 90’s and spent the whole time asking him about his Symbolics workstation next to him that ran LISP natively
@ricky865
@ricky865 2 роки тому
Are you going to do a ARM vs Power PC or X86 vs Power PC video someday .
@GaryExplains
@GaryExplains 2 роки тому
That would be interesting, but I think that it is too niche and wouldn't be that popular.
@WayneBorean
@WayneBorean 2 роки тому
Gary, as to Realms, Charlie at Semiaccurate says there are some issues with the implementation. Also could you cover the other ISA that are still in production.
@GaryExplains
@GaryExplains 2 роки тому
"the other ISA"???
@WayneBorean
@WayneBorean 2 роки тому
@@GaryExplains Sparc and Power are still going. I’m not sure beyond that, though I hear there’s some strange dev work going on in China.
@tortysoft
@tortysoft 2 роки тому
I was an Acorn guru... Archimedes was a tremendous computer. I wrote articles about it - sold in WH Smiths :-)
@jackm819
@jackm819 2 роки тому
Gary please cover the differences between RISC-V, Intel itanium, POWER ISA (openpower)
@GaryExplains
@GaryExplains 2 роки тому
That would be interesting for the real nerds, but since Itanium is basically died, I don't think it would be that interesting to a wider audience.
@Teluric2
@Teluric2 2 роки тому
Itanium use a very long word ops and risc is smaller , itanium is still used on Hp mainframes.
@perforongo9078
@perforongo9078 2 роки тому
@@GaryExplains The issue would not be whether Itanium is interesting, but whether hearing about how Itanium works would be interesting. I think it is.
@SmilerOnline
@SmilerOnline 2 роки тому
I'd be interested in seeing a comparison of RV & MIPS, as I think that ARM has reached a point where it now competes directly in some spaces to x86, where as RV looks more comparable to where MIPS was a few years ago (in comparison to ARM as a competitor back then).
@GaryExplains
@GaryExplains 2 роки тому
That would be interesting for the real nerds, but since MIPS basically died, I don't think it would be that interesting to a wider audience.
@SmilerOnline
@SmilerOnline 2 роки тому
@@GaryExplains Yeah, I can understand that. I was just thinking that perhaps it would be a useful way to help predict if RV will become a direct competitor to ARM one day, or if they'll go the same way as MIPS as there just isn't the same degree of interest in RV. My instincts tell me that the industry usually works best when there are two major competitors in each space, and I think that for now x86 & ARM have all of the attention from big industry players and RV is just used by a few companies looking to explore, but without too much commitment from them and so will probably disappear before x86 dies off.
@TorbjrnViemNess
@TorbjrnViemNess 2 роки тому
@@SmilerOnline Fun fact: MIPS is now a RISC-V processor designer - www.eejournal.com/article/wait-what-mips-becomes-risc-v/
@perforongo9078
@perforongo9078 2 роки тому
I actually think MIPS would be really interesting to hear about. MIPS powered the PS1, PS2, and Nintendo64. A lot of people alive played those consoles.
@racecar_spelled_backwards868
@racecar_spelled_backwards868 2 роки тому
So, is there any future in MIPS and SPARC at this point? I know there is an Android MIPS SDK, and MIPS is used in some routers, but very few seem to use it for main stream (long gone are the SGI glory days). I used to love SPARC stuff but Oracle has basically abandoned it. Is there any future with these or are they on their last gasp?
@TorbjrnViemNess
@TorbjrnViemNess 2 роки тому
The company MIPS is now making RISC-V cores, so I'd call that a decent indication of how the future of MIPS as an architecture looks (not great)
@crayzeape2230
@crayzeape2230 2 роки тому
The PIC32 line of micro-controllers from Microchip are MIPS based.
@diegonayalazo
@diegonayalazo 2 роки тому
Thanks
@stevenmsaxe
@stevenmsaxe Рік тому
Remember the IBM 360? It was the first company to design an architecture, including the ISA, then create a family of mainframes that that ran it. They ranged from small, slow and cheap (Relatively), to big, fast and expensive. The purpose was any program written to the ISA, would run on any of the mainframes saving bunchers of money and development time, mainly for business computing. Later on, Fujitsu, Hitachi and Amdahl created mainframes that were cheaper and faster, running the same architecture. The goal was for a program to be written once, that could run on any compliant machine forever. So far, it has made billions for IBM, and saved Billions in reprogramming costs. It sounds like Risc-V is trying to to do the same thing. The market is very different today. ARM has achieved most of the success that IBM had, but a program written for an Iphone cannot run on an Adroid without change, because the architecture is different. If someone big settled on an architecture like..... - Risc-v - UEFI boot - POSIX Complient OS (Like Linux or BSD) Then we'd see the a huge adoption. The Holy Grail of computing is to write a program, and have it run everywhere without modification. Risc-v could be a big step toward that goal.
@sgtnasty
@sgtnasty 2 роки тому
Didn't we go thru all this before with PowerPC? What is different now?
@GaryExplains
@GaryExplains 2 роки тому
Exactly. I cover that in more detail in my videos about RISC-V.
@sbn025
@sbn025 2 роки тому
Oh man you read my mind. I was asking myself that in The previous video.
@c434rdd410
@c434rdd410 2 роки тому
thanks for your detail comparing difference between risc and arm,let me know more about this new cpu ^_^
@RichardZak
@RichardZak 2 роки тому
Haiku supports (it’s working but rough around the edges) RISC-V, so there’s two OS options.
@catchnkill
@catchnkill 2 роки тому
Haiku is a small project with very slow progress. I installed the x86 version of Haiku beta under VMware months ago. Though it is a very old OS i.e. BeOS, it is surprisingly usable.
@law-abiding-criminal
@law-abiding-criminal 2 роки тому
With all these added instructions over the years, can arm still be considered a RISC ISA?
@jonwatte4293
@jonwatte4293 2 роки тому
No.
@bluesillybeard
@bluesillybeard 2 роки тому
I'm not sure X86 has literally thounsands of pages of specification, tons and tons of seemingly useless bloated instructions, enormous amounts of legacy stuff, etc etc. ARM is still much simpler, being much less bloated, but it's still incredibly complicated. I think it's probably not such a RISC architecture anymore. I don't know the details of each processor, so I can't give you a properly educated answer.
@xeridea
@xeridea 2 роки тому
From wiki "Most RISC architectures have fixed-length instructions (commonly 32 bits) and a simple encoding, which simplifies fetch, decode, and issue logic considerably." Basically, instructions are fixed length, significantly simplifying design, and thus increasing efficiency. Some instructions on CISC CPUs are multiple instructions on RISC CPUs, but the overall efficiency is much greater. CISC CPUs these days in practice take on this mentality. Instructions are broken up into smaller chunks, to allow higher clock speeds, and pipelined, multiple instructions being processed at once (not multicore, this is within the core), drawback of course is code branches, making accurate branch prediction extremely important. So RISC works on smaller instructions by design, CISC has complex instructions, and breaks them into smaller, wasting vast amounts of power with complex instruction decoding. Historically, CISC has had much higher single threaded performance, albeit at a higher power cost, but this gap is quickly narrowing, and where efficiency matters, reversed. Obviously in phones, efficiency is king, and with the M1, performance good enough for laptops.
@jonwatte4293
@jonwatte4293 2 роки тому
@@xeridea ... and in practice, ARM has thumb, RISC-V has RVC, and it's much more about how much an architecture can avoid or simplify complex architectural state in the speculation pipeline, than whether fetch/decode is complex. 30 years ago, fetch/decode complexity mattered, but not today. My question is: Does the approach in RISC-V pay off? What's the relative latency of a branch misprediction? How often does it run into a full pipeline flush? How much memory load pressure is avoided with the bigger register file? Those are differences that matter!
@xeridea
@xeridea 2 роки тому
@@jonwatte4293 I am not an expert on the topic, I know there are obviously optimizations with the fetch decode, but in general x86 is far more complex, and less efficient. It has came a long way, and has been cool to see AMD come back, in a big way, now we have lots of cores, which is another way to gain efficiency, due to how energy use grows exponentially with voltage/frequency. Branch misprediction latency is heavily affected by the pipeline length. Full pipeline flush would be.... anytime there is a mispredicted branch. More registers don't lessen memory load, they allow more parallel operations with the instructions. Bigger cache reduces memory stress.
@billchatfield3064
@billchatfield3064 2 роки тому
What about SPARC and PowerPC? They're RISC and have been around forever. Why can't we use them? Aren't they "open" also?
@ankiiths3274
@ankiiths3274 2 роки тому
can you please . . . name some tech company ( small ones ) w.r.t RISC,X86 and ARM based . . . reckon to become . . . a big company in future . . . in terms of investments for today . . . in your opinion thank you
@LordSoulSicarious
@LordSoulSicarious 2 роки тому
Are designers required to publish documentation on custom RISC-V extensions? Not the implementations, but the actual instructions and what they do. Because it seems like that would help with the fragmentation problem, as that would mean that even if a big player gets involved and pushes through a bunch of tech requiring their own custom extensions, at least the other designers could do a clean room implementation of those same instructions to maintain cross-compatability.
@Pulsonar
@Pulsonar 9 місяців тому
Slight confusion @ 15:00, about the difference between the RISCV hardware implementers - for example SiFive vs Western Digital? SiFive licenses their RISCV hardware implementation, but Western Digital doesn't, how does that workout for companies like Western Digital if other organisations can simply take Western Digitals RISCV core of the shelf for free?
@GaryExplains
@GaryExplains 9 місяців тому
That is a good question. I think the answer in the case of WD is that it doesn't care. It uses its RISC-V core internally (in the drive controller), it doesn't sell them as standalone things, and it doesn't lose any money if someone else does. So to make it look like an upstanding citizen of the open source community it can publish the design for its core and it costs WD nothing to do so.
@Pulsonar
@Pulsonar 9 місяців тому
@@GaryExplains ok, thanks for explaining so it doesn’t lose money. But couldn’t it boost revenue with a license model around its RISCV core IP like SiFive? Perhaps its pushing its reputation as an open source brand as you mentioned. Probably they are also monitoring to see if and how other companies use their unlicensed hardware for future business engagement that they can easily latch onto if it’s in a ‘hot’ industry application area that they hadn’t considered themselves.
@KC-gp4mf
@KC-gp4mf 2 роки тому
OS support does list iOS but list Android?
@tapiwamotsi1424
@tapiwamotsi1424 2 роки тому
You are too good bro
@GaryExplains
@GaryExplains 2 роки тому
Thanks!
@ronch550
@ronch550 2 роки тому
I think a good next topic would be high density libraries. If you look at AMD's Zen cores you'll see that everything looks like mush. Very interesting. It's probably the one huge leap in recent years with regards to chip design.
@RJLightning68
@RJLightning68 2 роки тому
Was the Acorn Archimedes ever sold in the USA???
@rosepark222
@rosepark222 2 роки тому
ARM's been around decades and mere 6 years old SiFive is just 5 years behind ARM? I would be nervous if I were ARM.
@kayakMike1000
@kayakMike1000 2 роки тому
You can implement the design in an fpga or emulator.
@danielstromberg
@danielstromberg 2 роки тому
There may be a misunderstanding about the subtle difference between opensource and copyleft-licensed software. TTBOMK, all copyleft-licensed software is opensource, but not all opensource software is copyleft. Opensource is a broader, more encompassing term that includes things like BSD and MIT licenses that do not require you to distribute source code if you distribute binaries.
@GaryExplains
@GaryExplains 2 роки тому
Indeed, the RISC-V ISA is free and open with a permissive license for use by anyone in all types of implementations. Designers are free to develop proprietary or open source implementations. Only the ISA is free and open, not the implementations.
@fbifido2
@fbifido2 2 роки тому
Has Microsoft made a Windows Core for RISC-V ??? or does WoA works out of the box ???
@obstinatejack
@obstinatejack 2 роки тому
thanks for the update, though there doesn't seem to have any real new event
@bkahlerventer
@bkahlerventer 2 роки тому
The strength of Risc-V is the fact that it allows extensions. A company such as NVidia can now add an extension for GPU instructions. However getting this more expensive Cpu/Gpu to run on the base risc-v instructions implemented will be 100% possible. The cpu maker members that formed Risc-V International designed and ratified the standards to allow precisely this because of the restrictions from ARM.
@ianboard544
@ianboard544 2 роки тому
This was interesting, but I am trying to understand why, outside of novelty and not paying ARM royalties, would anyone using ARM processors consider RISC-V. I primarily develop for ARM Cortex M devices and there are some features I like - the trace and debug facilities and the interrupt controller - are there analogous features in RISC-V?
@catchnkill
@catchnkill 2 роки тому
RISC-V is instruction set stuff. The features available for a RISC-V depends on individual design. There are a few public domain design for RISC-V already. Some are university projects. Some are very simple MCUs.
@ianboard544
@ianboard544 2 роки тому
@@catchnkill I understand that, but I don't pick an MCU for the instruction set. I just want it to be easy to use, with good compiler support and things like the interrupt controller and debug support that just work. Don't get me wrong - I like the idea of RISC-V, I just don't see the compelling reason (yet) to switch to it. So far, all I see is if you make millions of something every year and don't want to pay ARM royalties.
@THBek
@THBek 2 роки тому
What about IBM Power processors, isn’t it a RISC architecture?
@Teluric2
@Teluric2 2 роки тому
Yes its like sparc and mips.
@vincentvoillot6365
@vincentvoillot6365 2 роки тому
Beside the ISA and the number of register, all CPU use the same generic unit ALU, MMU/AGU, FPU, etc... What's matter is the instruction per cycle and with there popularity X86 and ARM have highly optimise scheduler, branch prediction, cache logic and both use a superscalar dual-issue architecture at least. Last benchmark i saw from SiFive couldn't compete with a raspberry pico (cortex M0). Western Digital "claim" 2.9 mips per mhz for Swerv EH1, between a pentium pro (3mips/mhz) and an athlon (4 mips/mhz on FX) and in multicore it's around 2 mips/mhz/core. Looking for a RISC to replace an X86 ? you can shop on ebay for a old DEC Alpha AXP (RISC 64bit) like a EV7, excellent IPS for a 25 Years old CPU :D (X86 emulation in bios as fast as a pentium pro)
@BeaglefreilaufKalkar
@BeaglefreilaufKalkar 2 роки тому
Well, one thing,, Apples SoC are compliant to ARM, that doesnt mean that ARM compliant SoC are compliant to what Apple Makes. It only means that the ARM instruction sett will run on an Apple SoC, but the Apple SoC are very much more that just the ARM intstruction sett.
@abstractapproach634
@abstractapproach634 2 роки тому
The big difference is that if you design a kick *ss ARM architecture, you have an entity that can pull the rug out from under you. (Like if you challenge Nvidia maybe) But if you prototype a kick *ss riscV chip, it's yours. You can share it if you want, sell it if you want, or both. That will encourage more architects to be drawn to it. So far we're talking very specific people with access power and skill set (that's the asterisk in riscV is open source*) but more of them can try, and that's good. Plus, with emulation, it may be possible that some sevant teenager from Nigeria uses riscV isa to make am amazing prototype plan, and that plan is his unless he chooses to forfeit control. Otherwise he could be strong strongARMed into giving up for pittens to the powers that be because he doesn't have the rights to use the ARM isa.
@obstinatejack
@obstinatejack 2 роки тому
like how huawei was kicked out of the whole arm ecosystem
@abstractapproach634
@abstractapproach634 2 роки тому
@@obstinatejack I'll have to look that up. What comes to mind is the linux on mac project, maybe that's right but it may just be a similar name.
@catchnkill
@catchnkill 2 роки тому
@@obstinatejack not true. nothing like that. huawei can still use ARM instruction set. they cannot find companies to manufacture their ARM chips in advanced process technology only. in fact huawei will sell new phones early next year using Qualcomm SoCs. those Qualcomm SoCs are ARM chips
@thomasvilhar7529
@thomasvilhar7529 11 місяців тому
I will try to use RISC-V this summer for some projects. This is due to better cost and performance a. Now I am using Attiny and STM, normally 8 bits. I will try for example CH32V003 for 15 cent with 32bits, higher speed etc. I am sure there will be a lot of new chips in this segment and the tool chain will come as open source. This is huge especially if you are on Linux like me since STM's support for Linux is really bad and Attiny not as economical.
@GaryExplains
@GaryExplains 11 місяців тому
Better cost and performance? I don't think so. I have tested the performance of RISC-V microcontrollers and they are behind Arm controllers (see my videos here on this channel). A Raspberry Pi Pico board is $5, and that has a dual core processor.
@alexanderwingeskog758
@alexanderwingeskog758 2 роки тому
My experience only... But ARM was a CPU, turned "Microcontroller", turned into a CPU/Powerful microcontroller, and then into a full blown "computer". Some people who design stuff still wanted a easy microcontroller for stuff. And I guess RISC-V could get back into that segment and then do a ARM transformation again to actually compete in the same market as ARM does today... with all the bells and whistles. I do know that you could still buy a really simple "ARM" compatible Micro controller type of chip ofc., But maybe for smaller company ARM might be a overkill and RISC-V might be more suitable?
@crhu319
@crhu319 2 роки тому
the fact that it's NOT OPEN SOURCE HARDWARE is important. The hardware design can and usually does incorporate proprietary elements. It will take a lot of work to create a competitor to the ARM ISO based stack, and that work could be undertaken by a lot of conflicted parties (governments and militaries, huge foundry corporations). So it's actually SiFive that has a processor, just like ARM, that needs to be commercially licensed. Other companies can do this too based on RISC-V, so they're not starting from scratch, and the compilers would be targetting something very similar to SiFive's CPU, so it's harder to sustain a monopoly and that monopoly won't be on the instructions themselves. Source code can be completely closed, as long as the instruction set is implemented.
@jdh30
@jdh30 2 роки тому
"Raspberry Pi uses a 1.5GHz" Raspberry Pi 400 was released in 2020 and already ran at 1.8GHz. FWIW, Acer Spin 513 (Apr 2021) has a 2.1GHz Arm CPU and the Apple M1 in their Mac Books and Mac Mini currently runs at 3.2GHz and is due to be superceded next month. I looked at RISC V alternatives recently for fun and they're all dire in comparison. I'd guess 10x slower than the M1 and 10x more expensive than other Arm boards. In contrast, HiFive Unleashed to HiFive Unmatched took 2 years so I think they improving a lot slower as well. RISC V is an interesting idea but I'm not expecting any disruption here. Maybe the MCU market but RISC V prices are way too high to compete there.
@ernestlane
@ernestlane 2 роки тому
Where does AMD fit in your evaluations?
@GaryExplains
@GaryExplains 2 роки тому
In a video about ARM vs RISC-V?
@JelloPuddingMaster
@JelloPuddingMaster Рік тому
18:33 the point about EEE (embrace, extend, extinguish) is moot: the whole idea of the RISC-V project is to allow anyone to manufacture a chip with similar enough ISA to not have to re-engineer or relearn the wheel while allowing for cut down options for lower costs/power consumption. Even if someone like Microsoft made an extension for something like hashing or other cryptography and a lot of big companies use it it doesn't mean everyone has a use for it or that everyone _has_ to use it. Sure, Microsoft's proprietary bitcoin miner might not work on your RISC-V based processor because you didn't license their extension, but what does a pachinko machine have to do with that?
@GaryFuller
@GaryFuller 2 роки тому
I'm curious as to why Quad-Precision Floating Point numbers aren't included in G? Are they not commonly implemented?
@geoffstrickler
@geoffstrickler 2 роки тому
Significant extra hardware, that’s definitely not needed for many embedded systems. This is the reason FP processors used to be separate chips from the primary CPU.
@jonnyjon2884
@jonnyjon2884 2 роки тому
I'm all for diversity, but what's the benefit of another RISC architecture, keeping in mind the current difficulties with price and performance? Great video Gary!
@SimGunther
@SimGunther 2 роки тому
That's like saying "why reinvent the wheel" when you should be asking "why not another wheel that's better at going over this terrain". R&D and QA are super expensive for CPUs which is why only the biggest of the biggest companies could take base CPU specs that are made either in house or by ARM and other syndicates to make their own RISC/hybrid CISC+RISC CPUs. They got their own specific problems they'd need to solve quickly with low power consumption and hardware changes seem to be the fastest (not really the cheapest) way to do so.
@jonnyjon2884
@jonnyjon2884 2 роки тому
@@SimGunther thanks, fair comment. Just trying to understand it all👍
@aliuzel4211
@aliuzel4211 2 роки тому
An enthusiast can implement soft RISC-V on FPGA and customize according to their needs. What about ARM ?
@GaryExplains
@GaryExplains 2 роки тому
True. Great for an enthusiast, but useless for anything practical. Also, there are plenty of soft CPUs out there.
@aliuzel4211
@aliuzel4211 2 роки тому
@@GaryExplains I don't agree with you. Developments on RISC-V denies what you have thoughts on RISC-V. My coin-sized 2,3cmx2,5cm FPGA test board will have 32-bit RISC-V, RAM, FLASH, MIPI DSI, MIPI CSI and be ready in mid December and I hope it will draw attention.
@GaryExplains
@GaryExplains 2 роки тому
First kudos for developing that board. As an enthusiast project, that is great. But what does your coin-sized board give the world that we can't get already from the myriad of development boards that exist for ARM, ESP32, PIC, ATmega?
@fuseteam
@fuseteam 2 роки тому
RISC V -> Berkley -> source code doesn't have to be released me: ah yes the BSD license
@fuseteam
@fuseteam 2 роки тому
@Coz Fi looks like someone didn't get the connection: - both RISC V and BSD originate at berkley - both RISC V and BSD don't require derivatives to release the source code
@davidca96
@davidca96 2 роки тому
@@fuseteam I gotcha 😉
@fuseteam
@fuseteam 2 роки тому
@@davidca96 nice :3
@bonzo-er6ly
@bonzo-er6ly 2 роки тому
Price/performace ratio remains critical to the success of either architecture. RISC-V has for sure the chance to surpass ARM because of its more modern basic design. But of course, somebody has to do it. Intel buying SiFive might be the critical mass to make that happen ...
@lhorthy
@lhorthy 2 роки тому
Please define your acronyms. What are ISA, ML, MTE, and DSP?
@GaryExplains
@GaryExplains 2 роки тому
Sorry that you didn't know those particular ones. I am sure you can find them with just a minute or two on Google.
@DavidStrube
@DavidStrube 2 роки тому
@@GaryExplains Surprisingly unhelpful response, Gary. You could've taken a moment to explain some of the more obscure parts of your explanation, but instead you chose to answer "Google it.". How very 27B/6 of you. Here, I'll take a stab: ISA: Instruction Set Architecture? (or International Society of Arboriculture) ML: Machine Learning? (or Multiple Lemurs) MTE: Multiple Terminal Emulator? (or Microsoft Technology Expert) DSP: Digital Signal Processor? (or Delaware State Police)
@GaryExplains
@GaryExplains 2 роки тому
@@DavidStrube LOL. Well done for misunderstanding completely.
@williamdavidwallace3904
@williamdavidwallace3904 2 роки тому
How about vids on east coast RISC from Austin Texas
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Gary Explains
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Snapdragon 8s Gen 3 vs Snapdragon 8 Gen 3
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CNBC
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SiFiveInc
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