Abstract:
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The down scaling of semiconductor technology throughout the past decades has led to the emergence of non-negligible leakage currents in Integrated Circuits (ICs). These currents cause an undesired power consumption in computing hardware even in the absence of computation, for example during idle or standby times. Worse yet, leakage currents act as a side channel and reveal sensitive information to adversaries who have physical access to security devices and wish to extract internally processed secrets. Previous works have shown that it is indeed possible to exploit this side channel for key recovery attacks against cryptographic hardware manufactured in nanometer CMOS technologies.
In this work we report the results of a long-term study on the subject spanning over multiple years and involving a sizable amount of resources and engineering effort. In particular, we designed, taped-out and analyzed custom ICs in four different nanometer CMOS technologies, namely 90nm, 65nm, 40nm and 28nm, and benchmarked the vulnerability of identical AES co-processors on the four chips to static power attacks. Our results show clearly that the susceptibility of the AES implementations depends directly on the feature size of the underlying IC technology, with attacks on the 28nm node being most powerful. These results show an evolution of the static power side channel which is undesirable at best, highly dangerous at worst for designers of security critical hardware in modern technology generations. Hence, we argue that leakage currents cannot be neglected anymore when certifying the security of embedded devices against physical adversaries.
#sidechannelattack #hardwaresecurity #cmos #hw_ioUSA2023
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