One thing that never changed for the last few years was A55... Finally a replacement found

1) add the 3 Gary Explains uploads to the watchlist 2) get a nice coffee & watch 3) ... 4) profit!

The unified FPU reminds me the AMD bulldozer era, but now in more suitable use-case for it.

Finally.. Our imaginary A58 is here 😅

Another great video explaining real things. This was a really great watch 👍🏻

I clicked faster than cortex A510

I imagine we might see a quad core version of this on the next RPi.

Thank you for your videos about ARM's V9 its easy to understand

Thank you so much for this video 👍🏻👌🏻✌🏻

Tbh the specint performance vs. power graph is kind of dissappointing. Considering the A55 is a 4 year old core and is largely behind what apples efficiency cores are putting down for example, the improvements arent that big. They largely trail the A55 curve and extend to higher performance levels, which to be fair can lead to good efficiency improvements depending on the workload in a whole soc. But even considering those improvements materialize in use cases, I would have expected more from this new Arm core design after 4 years of A55.

Gary , you the man, the tech guru !!!!, always look forward to watching your videos, superb once again.

6:15 Sounds similar to AMD FX series CPU. Two core shares one FPU.

reducing the area is a good thing and floating point unit is not mostly used in mobile environment

I really love this channel, he gives awesome contents

What is the maximum clock speed of arm cortex a510?

Question about the figures presented at 10:47 A510 vs A55. Are those percentages irrelevant of the manufacturing node ? Will there be the same +10% perf or -20% power usage in 7nm, 5nm and 3nm classes of manufacturing nodes ? Or it's just specific for a m. node ? Or these cores are designed for a specific single m, node anyway and my question is stupid ? Also, can I derive that the minimum power usage (the idle power ?) is higher on A510 ?

What about Matrix SIMD instruction for supporting Deep learning neural network efficient implementation ? is there any chip vendor that has already included these instruction as part of it's instruction set ? similarly to intel AMX instruction set ?

Mr. Gary, sorry to be the grammar nazy-like person around (I do lean in that direction) but in the beggining when A510 is compared to A73, it's not within 10% in "performance". If it's having 90% as much IPC and 85% as much clock frequency then it should have .9 * .85 = .765 meaning 76.5% of the performance of the A73. At 65% power usage.

Please make a video about Pixelworks Iris 5 and does it matter for devices with high end chipsets like Snapdragon 800 series.

So. The way the core complexes work is a lot like AMD's "8 core" FX 8350?

Would it be possible to make out of order efficient cores? IMO to keep power usage minimal ,can Take the advantage of advancement in manufacturing process and more L2 cache .

*GARY!!!* *Good evening Professor!* *Good evening fellow classmates!* Stay safe out there everyone! Two days off back to back may give me the time I need to catch up on my studies.

Energy consumption is everything in mobile SOC , display , camera ..... Out of order power efficiency core may be on 3 nm technology.

Can you explain Sifive P550 plz

Finally!!

finnaly!

Sir Using all apple products plus points and there plus points. Can arm can design apple level processor? Is there will only one limitation which is cost?

Finally! This will benefit battery life a lot 📱 🔋

How does the processor decide which task will require more compute, and hence needs to go to the high performance core? From what I understand, instructions are sent to the processor sequentially, one (or a few) at a time, so the processor wouldn't know in advance if the incoming instructions require high amount of computation.

Do the performance improvement figures also take into account new nodes? Or those are pure design improvements?

You say the merged cores share an “LTB”. Do you mean “TLB”? I’ve never heard of LTB I think, but a Translation Lookaside Buffer could make sense. Or does it mean something else? If so, what? :) Sharing a TLB sounds like something that could cause concurrency issues though if the operating system isn’t prepared for it. If one thread changes something about a shared memory region and doesn’t get the TLB flushed before the other thread tries to access it

Although many armv9 chips have been introduced today, what is visible is basically running apps in armv8 compatible mode. Only when Apple made the armv9 chip did it begin to showcase the new features of armv9.

But Gary, what is the performance and energy efficiency percentage increase of the Cortex A510 from the A55?

Cortex X2, a710 and a510 are leap upgrade soo,, should i upgrade my 3yo entrylevel phone this year or next year (??)

Yes actually I have that phone from 2017 in my hand right now

I'm really happy with 510 finallyyyyyyyy a new power efficient core I hated A55

3:37 i'm assuming this comparrison also uses the same manufacturing node for both processors 6:21 Ah, so its sort of like AMD's bulldozer, but not marketed terribly

As a tech nerd who owns a copy of "Computer Architecture: A Quantitative Approach, 3rd Edition" that I bought for a computer class on chip design, I really have to despise ARM on their butchery of the term "architecture" in their consistent misuse of it. The proper meaning of "architecture" is really what they're describing as an "implementation". It's the internal design of how a processor works. The correct word for what they're describing is Instruction-Set Architecture or "ISA" which is which instructions they support although strictly speaking, it's a little more than that because their ISA revs sometimes have more implications than just the supported instructions. For example, the THUMB instructions which were added for tighter code also include a special mechanism for switching the decoder into THUMB mode which describes semantics for the mode switching. But still, overall this is better described as an ISA bump because it's mostly about adding new instructions. ArmV9 is an ISA and the Cortex-A510 is an architecture that runs that ISA.

Near sd835?I thought the dimensity 800 is already at that level I believe this will surpass it Considering i play ppsspp and citra game aswell as codm & mobile Legends I think this should be a good $199 phone with mali g510

Woah. This A510 is better than A73. Yet companies are dumping A53 based processor like Helio G25, G35 and P22 even in 2021 in India. & A73 based Snapdragon 460 and 662 😣 Anything below Cortex A76 + A55 should stop selling now.

5:03 Hmmmm... 🤔🤔 Sounds a bit like bulldozer. Well at least it's only in energy efficient cores, so who cares...

Exynos 850 still using 8 core of a55, and it's already 3 years old Hopefully samsung will create new chipset using 8 core of cortex a510

This is sounding a lot like AMD's Bulldozer architecture. It was a brilliant idea but Microsoft didn't change their operating system scheduler to accommodate AMD's design.

So..as the performance is a bit higher than A73 core..i wonder if upcoming smartphone Soc there will be all A510 quad cores..as same as SD 625 back then which using power efficiency cores in its build..must be quiet a budget Soc in terms of performance and power saving..

8x A510 will rule low end smartphones

According to Anandtech, this isn’t very impressive. Very little actual performance increase. The v.9 instruction set is more important.

6:00 I'm getting bulldozer vibes

Watching on a device of 2+6 A75/A55 😅

10% less IPC and 15% less frequency means 23.5% less performance, the 35% power saved is not so impressive like that.

Hold on there... 10% reduction on IPC, 15% reduction in frequency = 76.5% the performance. Surely dropping the frequency of the older core to match that performance would save more than the 35% power efficiency "gain"? Seems like a useless product. Unless the footprint is much smaller or something.

Couldn't Apple simple adopt Risc-v and add the Arm instructions?

A bit over 10% better efficiency when doing the math than a BIG core from THREE years ago? What the actual f? How does that make any sense?

.

Only 35% less power? That's pathetic. A76 is more efficient

1st

hmmm hopefully won't work like AMD's disastrous Bulldozer uarc

finally there's a replacement of A55, and guess what, it took almost a decade to make one,.. huh.. nice work, no wonder why Apple is far ahead of the competition. Now there's that freaking M1, if they managed to squeeze it into an iPhone, it's GAME OVER for all manufacturers, including Qualcomm, Samsung and Mediatek.

Man after watching y videos about this subject, I am never buying phone without new cores and GPU. If ARM marketing is at list 70% correct than, it is really dum not to w8 1 year if y can, for new generation.