This is the only video on youtube right now that explains the actual concept in such easy manner.

This was such an amazing video, the last 15 seconds of analogy summed up everything for me!! Thank you so much🙏🙏

Thank you for this quick explanation. The analogy at the end was perfect.

This was fantastic. I'm an EE/CS... very clearly explained.

Excellent!!!!!!! No words literally!

your explanation on the subject just gave me a way better understanding in the item I was struggling to fully understand, your awesome thank you!

very well explained and easy to understand. much better than other videos available on youtube

Nice video Keep working on it. It's very helpful for others. Thanks.

very nice analogy! thanks!

Great video with a very clear explanation, thankyou so much you are a great teacher.

thankyou so much.. you made understanding easier .. 👍🙏

the analogy is perfect !

clear concise informative thumbs up!

really helpful!! Thanks a lot😄

Great video! But why internal cache is faster than external cache? Is this because, external bus to carry data is slower than internal bus? Like external is AHB where as internal is AXI?

A cache should be larger than a register file (i.e. there are many more memory cells in the cache than there are registers, so the signal carrying address of requested cell is 1) longer (for example 16 bits instead of 4 bits) and 2) has to pass more logic gates, mainly multiplexers / demultiplexers, until the signal gets to its destination. Or maybe it has something to do with cache coherency? Let's say there is some hardware element that ensures coherency of different caches; then there should be times when the cache is locked, because coherency-ensuring element is updating the cache right now, so CPU has to wait until it's over, otherwise it would get incoherent data from the cache. Or the cache could be implemented with slower and cheaper technology; for example if the registers are built on Nand gates, and the cache is built on capacitors like DRAM. Though I think all CPU cache today is built with logic gates and not capacitors..

Awsome content❤🔥🔥, very well explained. Would it be possible for you to make a similar video on how the data/address actually flow from the memory to cache and to the general purpose register, in detail?

Good analogy and explanation could u give the reaon why registers are ruicker to access compared to cpu cache? (other than physical distance)

Great video!! Thank you!!

Great video, thanks!

Awesome, thanks!

Thank you!

Great content Thanks

It was a great explanation

Wow very nice Video, thanks 👍

nice mam.....good explanization

I have Question about RISC.. There is a Difference between Risc and Risc-V??? Plzz Answer this. And make a vedio on Block Diagram of Risc-V.... Plzzz

good explanation...

0:45 This was the question I wanted answered

You deserve credit for me passing Comptia a+ 🙏🏼

Bz the cache memory is highly storage as compare to Registers so its rule that in highly memory fetch data is hard as compared to low memory

So, when cpu requests data does it first checks in registers or in cache??

Well done from Pakistan.

👍

Regiter s close and small memory that is why fasr

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I'm studying for SSC CGL but getting nothing 😢

You didn't discuss whether register is fast or CPU cache