Von Neumann Architecture and Harvard Architecture

Von Neumann Architecture and Harvard Architecture | Computer Architecture

Рік тому

In this video, I have explained the Von Neumann Architecture and Harvard Architecture.
I have covered the blocks or units of both the architectures and included an explanation of the Instruction Cycle (Fetch-Decode-Execute) as well.
You'll also be able to understand the stored program computer concept.
Each architecture comes with its own set of advantages and limitations which are explained in depth.
You will come to know about the applications/uses of both architectures.
In the end, there are two questions, check if you can answer them!
Check this video on RISC vs CISC processors: • RISC vs CISC | Compute...
Modified Harvard Architecture will be covered next!
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КОМЕНТАРІ: 26

@k283 Рік тому

1. Since instruction pipelining may require simultaneous access to both data memory and instructions memory, it is hard for pure von Neumann architecture to achieve that.. But if you cache the instructions and data (thus creating a small "ROM" and "RAM", respectively), then it can be done with von Neumann architecture, though this will be closer to Harvard.. 2. Simple branching and loops should be possible to build with just hardware, transistors. For example, we can implement branching using multiplexer - demultiplexer gates, which physically activates or deactivates different parts of the chip, thus altering the output of the chip; that can be branching... Or take a simple counter, that counts from 0 to 9 and back to 0 with intervals of 1 seconds - it can be the example of loops. No program needed, not even fixed one; a certain way of wiring the hardware parts together in this case is the program itself..

@BinaBhatt Рік тому

Thank you for the comment! 1. I agree with that one. And my next video will cover cache related info! 2. Actually, transistor weren't present at that time. We are talking about the days of vacuum tubes!

@ArneChristianRosenfeldt 6 місяців тому

@@BinaBhatt the architectures did not get their name at the time, historically. Naming is hard, so later we took the slightest indicator we could find. Already the Turing machine only has a single tape for “code” and “data”. Von Neumann merely stood up against those managers which wanted to save a few tubes and pennies and let women plug cables for their “program”.

@kayakMike1000 6 місяців тому

@@ArneChristianRosenfeldtHarvard architecture was invented by IBM, back when Big Blue was cool... They stored their programs on punch cards, writing data back to a punch card wasn't practical.

@ArneChristianRosenfeldt 6 місяців тому

So you say that no data was supplied on the punch cards? I recall that a lot of computers were wiped clean for the new job, and both code and data had to be supplied "in paper". I don't think that code was ever executed directly from paper. You cannot jump backwards. The reader goes through the stack from start to finish. Some programs kept part of the core memory and overwrote the other part with the next paper stack. And yeah here mostly data was kept in core memory.@@kayakMike1000

@kayakMike1000 6 місяців тому

Von Neumann architecture was an interesting insight that instructions were just data. The Harvard architecture was invented because IBM just wanted to use punch cards for ROM.

@ChristopherMutti Місяць тому

Great exaplanation ,like from zambia Unza 🙏

@iwonazwierzynska4056 9 місяців тому

A great explanation! Thank you!

@marutjarut6447 Рік тому

Please add, video about booting process of microcontroller and steps after reset.

@ArneChristianRosenfeldt 6 місяців тому

DRAM and SRAM are both used to store the internal state. Data flip flops also. These fabricated bias free ( TTL as a pull up bias, though), to store information as long and with as low energy as possible. So on power on ideally we have random values every where. Power goes through capacitors and comes on slowly. So outputs need to be disabled for some time. While reset is pulled the instruction pointer needs to be pulled to 0 . 6502 is pulled to cycle one of a multi cycle instruction. Then like a crowbar on release it looks up a vector at FFFB or so. Hmm, while the reset pin is pulled, the clock should drive a circular counter which resets all registers on the bus.