"let's go way back in time".... What, to when I'd already been a professional programmer for 10 years? ;)

What was the TOPS for AI int8 on an 8core x280

And this is why NVIDIA and Western Digital want RISC-V cores in their stuff, the ease of development. Plus, the instruction set is design for extremely simple decode logic, using set shifts from instruction encoding to registers for immediate instructions, directly wired register selection from the selection, a single location for sign extension bit.. so you can make a 15k gate, 32 bit processor with the embedded 16 or maybe all 32 registers. Even compressed instructions are just a direct LUT to an existing common base instruction.

Fallacy!

Looking forward to seeing RISC-V dominance in data centres at the end of this decade.

Nice video, well done, thanks for sharing it with us :)

Slides from SiFive website: sifive.cdn.prismic.io/sifive/25f3cf28-47ae-4cea-9e64-ecd43dea7f11_An+Introduction+to+the+RISC-V+Architecture.pdf

Where is sifive gpu ? Most people dont understand that this ip business model is based on volume. Arm will rule pc and mobile in the next 20 years. X86 will rule the data center for another decade. Risc v may have the car industry. But it is still tiny compared to both pc/car/mobile

Maga rides again ahhh verdad cabrón hahahaha😂

No mention of VHDL nor that Wirth created hardware with his Oberon language way before chisel and this horrible python based stuff.

Great talk

What about Python support for RISC-V? Is there a fully stable and official Python interpreter specifically tailored for RISC-V?

Funny how most computer breakthroughs come from one or two people doing side projects. Transistor, DOS, Apple I, C, Unix, ARM, Linux, Debian, Risc-V, Rust. Really only LSIC the GUI took big teams and a lot of money.

and now mojo!

proud moment ...........( jahoor bhai) 👍

Nice overview, Drew!

Nice.

Tx. You helped me.

IF SSA used have you cross licecensed w IBM God bless Fran Allen

Now where I can buy a Sifive p670 board? Thanks

Thank you helpful

Can’t wait to get 100k cores in my desktop PC. 🚀

The Hifive Unmatched could've done with a full x16 slot instead of just the x8 PCIe slot. I had some ideas for a silent, wireless SSD NAS/Access Point but the connectivity is limited, especially for the asking price.

No bloat, no backdoors you don't need, SiFive is fast enough to make #DONALDJTRUMP feel great again

The worst kind of "powerpoint" video. We can read slides. Reading them to us is of no help.

Interesting. So it's not an open source core itself, just an open standard. Any vendor can take it and use it for their proprietary chip. Are SiFive chips fully open source?

How to update bios in intelaken platforms

Good luck sifive. You are in right direction

Very interesting idea 👍

Sifive can beat apple m2 chip ?

HOPEFULLY they all decide to make professional level documentation that shows ALL the relevant information for the ISA in ONE PLACE not scatterbrained throughout one or more documents. As an example FLQ : RV32Q : I-Type | Imm[11:0] | rs1 | 100 | rd | 0000111 | blah blah blah description blah blah blah Showing the mnemonic, the opcode type, the encoding the opcode level and the encoding ALL IN ONE LOCATION not a little piece here, a little bit over there, more info scatterbrained through 2 or 3 other documents... ad infinitum. Look at the Sifive U74 documentation and they start out really well giving all the info in one nice concise blurb... but even here they often show an incorrect number of bits for many different bit field etc. More often than not they dont even state the encoding type (R Type, I Type etc) or even give the encoding at all. NOT HELPFUL!!!!!!!!!!!!!! Risc-V documentation is HORRENDOUS to the level where it is obvious that they cant be bothered to do the job justice. The one thing you can always say about ARM and Intel is that their documentation is SPOT ON. Everything you need to know about a given opcode is stated all together. Sometimes in many different locations. Risc-V documentation is a crap shoot cluster bleep scatterbrained totally unprofessional nightmare.

I cannot wait until someone develops a RISC V server core and we get away from the x86 duopoly that AMD and Intel have right now.

RISC-V will benefit China more than anybody

A visionary and an icon.

good job !!!

If there is one important thing, we have experienced in IT history, when it comes to adopt new standards, it is the need for backward compatibility. Remember many examples like the Z80, which only could gain ground because of it's backwards compatibility. Remember game consoles to desktop computers like XBox 360 Emulator on newer game consoles, Rosetta 2, windows Arm x86-64 Emulator. IOMMU is certainly a right step. But RISC-V urgently needs a good backwards compatibility solution to x86-64. Without that even intel failed to replace x86 with itanium.

RISC-❤️

I'm looking for standardized PC systems with RISC-V for that the majority of the Linux Distribution can support. I am looking for ATX motherboards or comparable boards with standard boot loaders and other standardized interfaces so that the system can also prevail outside of the nerd corner.

The RISC-V has ni Future! The RISC-V does not contain innovative ideas in microprocessor design capable of replacing existing processors such as x86 and ARM. The RISC-V processor is not suitable as a candidate for this role. They say “RISC-V does not represent new technology”. The RISC-V has no novelty potential. The tomorrow’s world needs completely new architectural ideas as familiar processors x86 and ARM are morally obsolete architecturally. I propose the novel architectural idea, see my article, address is below in this comment. The RISC-V is good for embedded systems, controllers, and similar as free and open. There are other positives and improvements, but they are on the engineering level. But the RISC-V will never become a general all-purpose processor. The RISC-V is based on 40-year old ideas as RISC-V Foundation claims. There is no sense to port the huge x86 and ARM software ecosystems on it. Thus, RISC-V will never gain a victory over x86 and ARM. The most of positives about the RISC-V processor are arbitrary speculations. Actually, the main advantage/benefit of RISC-V is free and open architecture (open ISA). The RISC-V processor has instructions with variable lengths, consisting of 2-byte snippets. It is strange, it is bad being a deviation from the classic, absolute, and pure RISC principles well formulated at the beginning of the RISC era. Also the RISC-V processor has 6 instruction formats, and it is too many. The Contemporary microprocessors contain 8 specific hardware components: (1) SMT (Simultaneous Multithreading), (2) register renaming, (3) instruction reordering, (4) out-of-order execution, (5) speculative execution, (6) superscalar execution, (7) delayed branch, (8) branch prediction. These components make up some kind of a “magnificent eight” of components which essentially raise the performance of microprocessors. But unfortunately they are very complex. A processor core having these components is a full-fledged one, otherwise it is good for simple applications, e. g. for embedded systems, controllers etc. The “magnificent eight” of components is very hard to design, only the experienced firms and developers are able to do this, and much know-how was acquired, some effective solutions are patented. Particularly complex is the SMT. Only powerful and advanced firms like Intel, AMD, IBM are able to equip their processors with the “magnificent eight” components. It is not surprising that some Intel processors, and the famous Apple's M1 processor do not contain SMTs. If a company is able create the full-fledged RISC-V processor with all “magnificent eight” components then it would be a serious achievement, and such RISC-V would be considered of the World's class comparable with x86, with ARM, but not more. As far as I understand most of the developed RISC-V processors have no components from the “magnificent eight”, and are intended for embedded systems. A course directed on further development of RISC-V is a wrong way, and leads the computer architecture to deadlock. The RISC-V is not promising for computer industry. In fact, RISC-V hampers the further development of the state-of-the-art microprocessor technologies. The World demands absolutely novel microprocessor having much more higher performance than all contemporary ones. The novel and effective ideas on computer architectures do exist! Here’s such a novel processor architecture: V. K. Dobrovolskyi. Microprocessor Based on the Minimal Hardware Principle. Electronic Modeling, 2019, vol 41, No 6. pp. 77-90. The article is posted (under the Cyrillic name добровольский.pdf): www.emodel.org.ua/en/ then touch ARCHIVE, then move to 2019, then to VOL 41, NO 6(2019) pp. 77-90. You see: DOBROVOLSKYI V.K. Microprocessor Based on the Minimal Hardware Principle Click “Microprocessor based...” At the very bottom you’ll find Full text: PDF Click it. This processor does not have the “magnificent eight”, it is not necessary at all. This comment reflects different view on the RISC-V architecture, and the computer community has a right to become familiar with such a view. I’m Volodymyr Dobrovolskyi (V.K.Dobrovolskyi).

Interesting

Will RISC-V be better than Ryzen 7950X?

No gpu core ???

and one more question, if i want to a give input to freedom studio the compiler did not accept the input as scanf or Cin what should i do ?

hii i have a project in bachelor so my project is about RISC_V . i want to implementation a reed solomon codes on sifive. if i want to use an arm microcontroller instead of that what series i can bye ?

When can I get an ATX motherboard with RISC-V on it to use as a development workstation?

Gr8 Presentation

When on the slide @ 19:39 there is written Taiwan and not this crappy Taiwan (China) some bureaucrats don't like this at all.

Thanks Chris for a great talk.

does it provide annotation or tags for handwritten notes so you can search later by tag name?

I was at Google 3-8Y ago and noticed that language tools just didn't scale. gdb would take 60s to start on a 200MB binary (600MB with symbols) and often wouldn't start at all, or lost track of where i was in the program.