Are you studying at CSUN for your masters???

Wrong. You can make those interfaces with some FPGAs (not all), you can also have them in microcontrollers too.

@@conorstewart2214 prey tell, what MCU have >20gbps serialisers? Or at the very least an array of 2.5gbps LVDS links? Even getting a full speed 4-lane D-PHY on an MCU is a wet dream.

A few days to US. Up to 10 days international. I'm not dead! News soon...

Generish answer to a generish question: Use an FPGA for the signal processing and a microcontroller for the control logic. SOCs with integrated processors are ideal for such hybrid tasks.

Shipped today. You should get an email with tracking number.

​@@Nandland Just checked it and I got the email, thanks!

As well as the fact that programming the same things (uart, spi, i2c) takes considerably less time and rows in MCUs

I agree, it's a reactive programming model of computation that web developers keep wanting for a few decades now.

Ok

A “slice” or logic element is pretty much just a multiplexer with a latch chained after it. Look at any FPGA datasheet and you will see their layout.

Not if power consumption matters. FPGAs are very hungry. 😉

Except only 1280 LUTs and very little storage for $70, it is a very bad deal.

That's interesting. Can you elaborate on why FPGA verification is cheaper than software verification? FPGA verification is not exactly simple and quick. It usually takes longer than designing the FPGA itself.

@@Nandland In aviation DO254 and DO178 standards are used for hardware and software development respectively. In DO254 system level testing (black box) is good enough but DO178 requires unit testing (white box) which is apparently tedious and longer. Some good info here: afuzion.com/do-254-costs-versus-benefits/ Im not sure on how either testing is performed but thats just how I read it. Curious to find out more though.

I never worked in aviation but generally consider this a myth because in hardware you always have phenomenons like clock-domain crossing or timing issues which are very hard to debug. Not to mention that there are much too few competent hardware designers in the industry.

you can think of fpga as - readily available interconnection matrix on the fpga. As per the boolean equation of your written logic in HDL. interconnection matrix will be realized as a logic circuit.

99.999% of all electronic devices on this planet are sliced as chips from disk-shaped n-type or p-type silicon wafers, processed at a factory (called "fab") to make patterns of transistors and HARDWIRE them, using layers of metal and oxide (insulator). All these chips are called ASICs. A microprocessor is an ASIC. A GPU is an ASIC. Even an FPGA is an ASIC. But it's a clever one. Ross Freeman in the 1980s at Xilinx (now AMD) has invented an idea to wire up the transistors at ASIC's application FIELD, and so FIELD-Programmable Gate Arrays were born. ASICs are hard-wired at the fab. FPGAs are soft-wired at the field. To hard-wire the ASICs, we use Verilog (or VHDL) and special place-and-route methods to lay out the transistors and hard-wires on a 2D description of the ASIC chip (manual, traveling salesman, simulated annealing). Fab owns proprietary trade secrets of how to make actual transistors on a wafer. Everything below 130 nm is covered by NDAs and "top secret" access agreements (or non-commercial use university-accesses). The fab gives exact sizes and spacing between transistors so the so called "Standard Cells" can be used at the place-and-route process. To soft-wire FPGAs, we ALSO use Verilog (or VHDL), and very similar place-and-route (P&R) methods. But instead of waiting several months for creating a chip at a fab, we create a special "firmware" that's called "bitstream" and we can put all kinds of different bitstreams into the same FPGA indefinite number of times. Some FPGAs, connected to each other, can even reprogram one another, while working in the "field of their application". Both FPGAs and all ASICs run on a special model of computation that is different from CPU. It's a massively parallel computation of a forest of Boolean functions of many variables (sharing a lot of overlapping branches, otherwise there's not enough atoms in the Universe to compute anything fun). Each trunk of such a Boolean function tree produces a single 1-bit value, 0, or 1. In order to do all the magic we see around us, that single bit is stored inside of the truly magical device called D flip-flop. D flip-flop is crucial to understand the magic of FPGAs (and most ASICs). D flip-flop stores the PREVIOUS (old, "current") value of all computed variables, so that value can be fed into the forest of Boolean function trees. Each Boolean tree in an FPGA produces the NEXT value (new, "updated") value and feeds it into the "D" input of the D flip-flop at a special moment, when the "CLOCK" input of the D flip-flop changes from 0 to 1: the D flip-flop has internal double buffer to swap between the "old" and the "new" 1-bit values stored inside of it. The "Q" output shows only one internal buffer's value at a time: a special device called "multiplexer" (MUX) switches between one of the two buffers. In short, what FPGAs and ASICs do, for software developers can be summarized as reactive programming: en.wikipedia.org/wiki/Reactive_programming

Wrong. You can implement floating point in FPGAs, also a lot of microcontrollers don’t have floating point units (FPUs) hence are not good at floating point arithmetic. So with a lot of microcontrollers you don’t get any support from the hardware, but FPGAs you can implement floating point math if you need it and have enough resources.

@@conorstewart2214 the DSP slices in FPGAs are fixed-point. That's the only support for arithmetic operations you get from the FPGA itself. Of course, since an FPGA can be synthesized to almost any boolean function, you could implement a floating-point unit or use some IP core for that, but that would be an extreme waste of resources. Floating-point operations are usually done in software, typically on a softcore or hardcore processor built into the FPGA, which I personally do not consider as FPGA design since I'm a hardware developer. 😉

@@NoSpeechForTheDumb you can use the existing DSP slices plus a little additional logic to do floating point operations. It is generally easier to implement multiplication and division than addition and subtraction though.

@@conorstewart2214 the point is: even though you CAN do virtually anything in an FPGA since it's a reprogrammable integrated circuit doesn't mean you SHOULD do everything in it. If your algorithms rely mostly on floating-point logic, a dedicated microcontroller may be MUCH more economical since it is cheaper.

@@NoSpeechForTheDumb in just about every situation you would be cheaper to use a microcontroller, but if you are using an FPGA anyway there is nothing wrong with implementing a floating point math unit in it and if you needed to do lots of floating point calculations then you can do them in parallel.

2023 they are cheap, cheap enough that their “go board” is very bad value.

This is very typical of someone who speaks English, the problem isn’t with the video.