It's really hard to find hardware tutorial, there should be more hardware content in the world.

Thanks!! the world is in need of more fpga content!!

Hello. Greate video, thx for your work!

Thanks for the tutorial, but I think it would be nice to put an IP-core visual representation of this SPI, i.e. box with all i/o, etc listed within the code.. Should it be 2 SPI modules? Data comes from a source to TX on Master, then Master transfers it via MOSI to Slave?

God bless you !

Hi ! Can you suggest how to interface spi flash with spartan 6 to write and read user data

Can you please share the specs which you referred for developing code?

I am unable to simulate this code xilinx ise 14.7. please suggest me another one

Thanks for making this video, at 5:55, why does there need to be an extra delay for the output spi clock? Is it because you are using one cycle to copy the data on the input? also does the half bits per clock really need to be 2 or more? It seems like it would work with a value of 1 from looking at this EDIT: I see the need for delay for the output spi clk, it's because you are basing the output of the spi_clk on r_leadingedge which is already a cycle behind

Whats the purpose of " r_SPI_Clk_Edges" in the context of spi mode and no of bits to transfer in that SPI transaction

I want to ask another question. How to read the contents of the register in verilog through spi. We knoww the addrsss of the first register. Then the address auto inreements

How to convert SPI to I2C protocols using Verilog Code??

Hello sir, how can get this verilog code?

Thanks for the video! I have a question on how we should utilize or modify this code if we need to transmit and receive data 2 bytes at a time instead of 1 byte at a time as shown in the code?

What is the programming language you are using? Look like Pascal, but is not.

Thanks for really helpful video. But I have a question that how to make and send 'real' signal in FPGA. I mean, if I want to SS low at specific time how to do it?? not for testbench.

Two very basic questions 1. In MISO always block why you need to check the (o_tx_ready) signal.??? 🤔. o_tx_ready is the flag generated by the spi master to tell the upper module that its ready for next transmission on MOSI.. 2. In first always block where we are counting the edges of the master clock (i_clk) to generate the spi clock edges.. Kindly elaborate who the trailing and leading edges are correlated with this count?

can you send the simple verilog code for SPI

What's the function of the code reg [2:0] SCKr; always @(posedge clk) SCKr

Hi, you have sold this tutorial on udemy

I feel so hard, what ability do I need to understand?

$CLOG2 is giving error in synth

can we please all come to the conclusion that the programming language we use is C