I love that there are open source alternatives to Intel and AMD now. RISC-5 looks incredible for jobs where you need a custom designed processor real quick. It's also cool that you mentioned how many companies are investing in RISC-5 and integrating the technology into their own business models.

Somewhat surprised at the speed it is being adopted.

great video!

Could you implement de-essing software into your audio? It would dramatically reduce harsh SSS sounds which are very common when talking about anything electronics and make the video easier to listen to

I never would have thought that chip technology developments could be so interesting. You are able to communicatie complex things simply with infectious enthusiasm and true knowledge. Keep going, great work!

My experience was pretty much the same, except I didn't even bother with x86[-64] in the first place.

Great job! I'm also creating my own language with a fully custom IR and backend, and I will target RISC-V.

Have you done an ARM compiler?

No, unfortunately I have not looked into ARM so far.@@hieverybody4246

Hey now, you're an all star Get your game on, go play Hey now, you're a

Most people get it wrong. RISC-V is just open instruction set. It does not offer you open source hardware implemenation of the instruction set. There is a big difference with ARM. ARM can license you the hardware design as well.

I always see that ARM takes a fee for every chip made with their ISA. How does this work? Did ARM make this ISA and can now just get billions of dollars for it every year as long we all need these chips? If so it sounds like we would have more companies trying to design something like that? Or is it the fact that shifting to a new ISA is difficult because of the software that is written in code to use ARM only? So ARM basically had a homerun when it became the standard for most mobile devices?

@@maxjames00077 Your have already answered your questions already. It is difficult to design chips and thus many companies license ARM's design. ARM does not earn that much. Many ARM chips are low end chips and contribute to several cents of royalty per chip.

@@catchnkill ty bro

True, in the last 2-3 years it’s adoption is increasing so fast

The hardware is one thing, but the software is really a lot more important. If those companies make RISC-V chips too different from the standard then software won't run on their chips. There's no benefit to making entirely custom ISAs.

@@perforongo9078 The benefit is obviously that you get a jumpstart as compared to starting from scratch. But again - making custom risc-v designs, of which there are several already, lots of patents and shite, doesn't make the world more open.

If they break compatibility then they can't call it RISC-V. If someone does that then it's no more relevant to RISC-V than if they'd started from something like MIPS or designed their own from scratch.

@@BruceHoult Are you sure about this? AFAICS the BSD license doesn't have such clauses.

@@roysigurdkarlsbakk3842 The BSD license allows you to use and modify the specification without attribution, but you can't use the trademarked RISC-V name without passing compatibility tests.

Since the flaw is baked into the CISC hardware, you need to write browser code that does not call/trigger this CISC "feature". This is, not surprisingly, not being addressed by many browser companies, and many users do not apply security updates.

have you seen open source BIOSes?

The RISC V instruction set really is genius. And from extremely efficient use of program memory space on a low hardware footprint, less power, less heat to dissipate, less distance for signals to propagate permitting higher clock speeds, it's win, win, win. This is going to push software compiler development really hard to break apart traditional one-processor tasks to run concurrently over many RISC V processors. For example, OpenSCAD Programmer's CAD really needs it. ARM started with some genius designers but they have mainstreamed too much and forgotten their edge. A bit like a rock band with a great first album but then polishing out their quicks, loosing their flavour in their desire to appeal to the masses. The Acorn Archimedes with it's barrel shifter was revolutionary. That's a long time ago. It superceeded the 6502 which was also revolutionary with it's indirect addressing and intuitive assembler mnemonics.

The ISA is free to implement, but any implementation that's comparable in performance to a modern desktop or laptop processor absolutely will not be open source.

@@fluiditynz aarch64 was basically a clean break from older arm ISAs.

What are the advantages? The reduced set of instructions? Or that low-level language she mentioned? Curious. Also, can it replace general-purpose CPUs?

@@spyral00 it is a general purpose cpu, low cost, less power, better designed for current needs.

And even on that note, MIPS was better over time than register windows of Sparc, and also it was, at the time, pretty revolutionary to leave the branch delay slots for extra throughput by not interlocking the pipeline with auto nops. Turns out, they're bad for high end implementations, but it was still very neat, and the nicest of the various original RISC boom architecture. ARM2 was relatively elegant, but the barrel shifter was odd. Arm has gotten much more cluttered since, almost to the point of not being risc. If you want more IPS, fuse some instructions in hardware instead of adding more of them..

@@mikafoxx2717 I did the MIPS port to Linux and worked for SGI, MIPS Technologies and Imagination so I not only know a thing or two about MIPS but also my views may not be perfectly objective :-) That said, the branch delay thing used to be quite common Among others HP's HPPA (later renamed to PARISC) also had branch delay slots and a few others. I don't know where they originated. Branch delay slots basically are a nice idea as long as the pipeline is simple such as the five stage R2000 or R3000 pipeline which in theory can achieve one clock per cycle for most instructions. Notable exceptions are FPU instructions, integer multiplication and divide. With those processors the problem is to find something sensible to put into the delay slot. MIPS' own compiler was pretty good at filling delay slots but that wasn't always possible. And the assembler did default to reordering mode where it did put the instruction immediately preceeding the branch into the delay slot if there were no dependencies that is if the reordering candidate did not write a register which the branch instruction was going to read. Then came the R6000 which did introduce the branch likely instructions which only execute the instruction in the delay slot if the branch is taken. Basically an instruction designed as loop closure instruction. Bit of a braintwister for humans to use and much tougher for compilers as well. And hated so badly by MIPS pipeline implementors that still today they push pins into voodoo dolls of the R6000 architects. In a calm night in the silicon valley you can hear them cry for every needle. But only when the SPARC register window folks which are suffering the same voodoo needle fate are calm ;-) The whole branch delay slot / branch likely thing stopped being a big problem for out-of-order architectures which are able to reshuffle instructions anyway. That said, MIPS has turned from "real" computing to embedded and so the vast majority of CPU cores like the 4K, 5K, 24K, 25K, 34K series of CPU cores from MIPS Technologies but also cores like Sibyte/Broadcom's SB1/SB1A cores are in-order and thus the branch delay slotand especially branch likely slots pains (and the voodoo needles) continue.

Thank you 😊

❤

I think she was saying "edge AI".

I have one of these and it's super cool that I already have RISC-V in my hand. One of the other great benefits is that since RISC-V is actually popular, I can use the normal Rust compiler for compiling to the ESP32-C3 instead of having to use the unofficial Xtensa fork. Maybe one day we'll see the STM32 and other ARM-based microcontrollers replaced by RISC-V as well, there's really no reason to stay onto ARM at this point

@@NoorquackerInd I've recently replaced an Stm32f103 in a blue pill board with a RISC-V core CH32V203 (it has the same pinout and very similar memory map) running at 144MHz. Now I'm figuring out how to deal with the USB CDC mode. The IDE for this mcu is eclipse based (mounriver Studio). The main handycap that i find is that, although there is some guidelines in english, the vast community for the CH32V family of processors is in Chinese. But this could change sooner o later if this family gets certain fame (as the GD32VF similar one). Also take a look at the Ch582/3 family of RISC-V BLE devices.

@@Robbie-mw5uu I want them as easy to wear as sunglasses. Or contacts.

I don't think that low-cost manufacturing will be possible. Lithography masks are extremely expensive and even low volume would mean at least one wafer, which also costs thousands even on an older manufacturing process. While I suppose that 'never say never' applies for general-purpose masks that can be recombined to produce your custom chip, I don't really see that coming. There's just too many possibilities that need connections run between them somehow. I'm fairly certain that custom chips will remain in the domain of 'tens of thousands' units at minimum. (Not counting things like wafer-scale chips. Those might make sense at hundreds already. But that's the domain of ultra-highpower datacenter compute...)

@@Steamrick Well, you're probably right. But still it would be great to be able to get a few prototypes of your own design even if for a few thousand dollars (seems pretty cheap in comparison to no such possibility now). :) I think it is only possible if the interest is high enough for such a service.

The REASON for this "Prophecy" is not hidden. The USA MUST become chip independent again. That means finding alternative materials that we have on our OWN soil. *(Steps on soapbox)* STAY WITHIN OUT RESOURCE BOUNDARIES. *(Steps off soapbox)* That said and out of the way. RISC-# in general has not been accepted in mainstream, ever. I've been around for EVERY chip since the IBM 3500 into the 12th+ generation of CPUs.

@@Steamrick if maskless lithography develops further, it will be possible

And VEGA. It's nice to see unconventional countries making chips.

Have you missed noticing RISC-based iOS and Android phones and tablets grow over the last 14 years?

@@BruceHoult were you building computers in the 90s? Are you aware of the unfulfilled promises?

@@chrissinclair4442 Building, no. My main desktop PC and/or laptop was always RISC-based for a decade starting from 1994, and again now. I'm not aware of unfulfilled promises, no.

I don't know what you can do for analog (other than SPICE of course), but for digital you can run your RTL design at tens of kHz in Verilator, or at 100 MHz or so in an FPGA. SiFive used inexpensive Arty boards ($200) to debug their first FE310 chip and E31 core. You can also fit a single U54 or U74 core in an Arty, but to test the whole 5 cores plus L2 cache "core complex" for FU540 and FU740 a bigger more expensive FPGA board, the VC707, was used. For the still larger OoO cores such as U84/P550 a VCU118 is used. Those are pretty expensive boards, but much cheaper than making a chip. You can also rent Amazon EC2 machines with the same FPGA as the VCU118 by the minute, which is a cheaper way to get started. The VROOM project is doing that, for example.

Brings down the cost for who?

@@trtrhrfor people who want to innovate.

Which FPGA, out of curiosity ?

My implementation is all in verilog... It's actually kinda hard because a few of the instructions take a little longer than others, like accessing some of the memory blocks or external RAM/FLASH... So you gotta stall the core while the data comes in from the outside. Also, storing values out to RAM also can take a few clock cycles, so if you get multiple stores at the same time you gotta stall a bit then...

Basically endless amounts of glitching.

@@kayakMike1000 My implementation is all in trees... It's actualy easy to implement 16 (in my 35-years programming never more needed, all my programs is less then 16 levels trees) chains of commands , 1 chain for each level. And each level to be programmed separately , what i always do.

risk is good. I hope you don't screw like you type.

Oops, a typo :( 210 teraFLOPS

@@AnastasiInTech It doesn't look like written by you??? More looks like excerpted from their video of website or somewhere else???🤔

@@willykang1293 No, it is done by me