As Jim notes, RISC-V is just the latest clean design for basic scalar processor. Great if you want what he calls "baby computers" OR use as a control processor for big block of specialized processing like AI. Thus the natural fit to AI processor startup opportunity. The design focus isn't even on the scalar processor so just license the scalar proc implementation. Focus on the AI parts which don't use any of the traditional scalar processing tool chain (C/C++ compile/link/debug) nyways.

Keller isn't new to RISC architectures engineering: he worked on DEC Alpha (before it on the VAX 8800, which is a CISC ISA), MIPS and ARM SoCs implementations.

Developing software alongside the ISA will let you eat the cake and have it too ;)

when a person knows the craft, they don't need to bullshit :) I think any engineer that's been working for more than a decade can relate. Jim is clearly a master of his craft and knows from experience.

No way! Lmfao

@@Supermrloo high IQ roast, I see.

Problem is that there are SSE/AVX/AVX2/AVX512 versions of same instruction. Cray style vectors (and RISC V vector extension) enable exactly the same code executes on every CPU, change of vector length or number of execution units just change speed. Program vectorization is an old topic, Intel bought company which made such compilers 20 years ago. But in order that such technology work, ISA must have support. No scatter/gather operations? No vectorization of spare matrix vector multiplication. No vector masks? No conditional execution. More flexible vector ISA is, more applications can be vectorized. For applications with irregular parallelism OoO can handle it. Vectors are good as cheap way to have number of operations without having to made too wide superscalar (now) or to have simple instruction fetch while keeping multiple execution units busy (Cray 1). With x86 "same" instructions are not same at all, even simple move is actually few different op codes. And some normal instructions like jumps have crazy options, everything is documented in Intel's manuals. So it is far from just 8 instructions.

It's fun. Almost like getting a front row seat into the possible future lol

Most chips are already very close to RISK once your past the decoder. And even modern (x86) decoders don't require much modification to support other ISA's. But what is the point, you really don't need to support multiple ISA's and in the end, you optimize your design for one specific ISA.

There is no legal problem once these x86/x86-64 patents expire. :D

@@seylaw when will they expire?

@@law-abiding-criminal While some did expire already, unfortunately it will take a while to be practical: www.blopeur.com/2020/04/08/Intel-x86-patent-never-ending.html

@@seylaw Yes, there is. Not just patents. Intel's x86 is copyrighted. The copyright protection is expired usually some years after the death of the copyright holder. Since Intel will not die soon, the x86 copyright is there to stay for a long time.

Steam Deck is exactly that.

it's not exactly "old legacy and useless" it's more of "legacy base with newer features added on". Changing the old stuff would mean changing almost literally everything since needed changes will just ripple downhill. It becomes a chain reaction of "we need to rethink everything" and at that point newer instruction sets like RISC-V already have that kind of work done. Simply put, it just wouldn't be x86 anymore

They did clean up with AMD64, but older ops can be eliminated and emulated in micro-code. Modern chips pay more attention to running what is used today, obsolete instructions run slower.

It's not a dumb question at all. To Intel's credit they moved away from a strictly CISC architecture when they released the Core series. The actual cores are effectively RISC cores and a lot of stuff is translated or dealt with by other circuitry on the chip. So the instructions actually carried out have been cleaned up and are easy for the prediction. The idea that x86 is falling behind stems from the fact Intel failed to implement their new process node for years and Apple brought out a stellar chip. But Apple gained from leveraging custom accelerators and really wide decode, big out of order execution buffer etc. Which Intel can will do. The real gains from RISC are more about the ecosystem, licencing, ease of implementation etc. There's nothing wrong with x86 Intel just had a marketing guy steering the ship and AMD had no one steering at all it seems like.

Sorry, but the explanation sounds more like corporation politics and excuses for intel and less like a real unbiased technical analysis. CISC to RISC translation is not a clean up at all. RISC is indeed much more efficient and much faster, even faster than Keller claims. Apple's M1 is just one example for that. If the ISA really did not matter, our smartphones would be driven by x86 atom CPUs, but intel lost that performance per watts game too. Probably the biggest proof for the superiority of RISC is intel's switch themselves, by translating CISC to RISC in later CPU generations. Some people might still remember the Pentium 4 which was known for its very high heat output. After that the core design came out with much shorter pipelines than the P4's netburst. Branch and instruction prediction is not everything. The P4 was also an Out-of-Order CPU, but this increases the energy consumption. The solution was to step down to a less complex structure in combination with a better prediction. But what does hold back intel to switch to another ISA completely? Its because of the patents and compatibility. Apple absolutely made the right choice with the M1 and its x86 compatibility layer until they can leave behind old x86 completely. Also unlike intel they are in the position to switch and establish both, the OS and the underlying hardware. RISC-V has already landed in the industry, but there is still a long way to go. It needs virtual extensions and x86 layers etc. to dethrone x86 and finally bring more competition and innovation in the CPU landscape similar to the GPU market. In that sense I appreciate intel's step into the high end gpu market though, where they are finally forced to step up with more new ideas. But if there were no common API standards like vulkan etc. intel would probably play the same monopolistic cards like they do in the CPU segment for desktop pcs.

@@aladdin8623 I don't think that's necessarily true. Even some of the OG RISC proponents have said there's nothing fundamentally more efficient about RISC but the benefits come from all the (potential) architecture surrounding the cores. Apple's decode and buffers and cache etc. are massive compared to Intel's. They also put the rest of the memory etc. Very close to the CPU. Intel's and AMD's isn't even the same width and AMD's isn't even the same internally, and at different process nodes with different implementations of the same ISA they've produced equivalent performance to Intel. I think that speaks to how arbitrary it is. The whole calling card of RISC is fixed instruction length, and Intel implementing 'risc' cores let them do all the complicated reassembly of everything coming out of the other end of multiple cores, and then again with hyperthreading. It let them optimise the prediction. So in theory, they're at no fundamental instruction-length disadvantage. And it's not particularly simpler apart from that. It was Jim Keller himself who said ARM's and MIPs and whatever other ISA is unfathomably complicated. Comparing Apple's Intel models with a single Apple SoC would have been like saying CISC is inherently better because IBM's Power architecture couldn't keep up in 2006. Even with Apple's amazing job the cores themselves aren't THAT powerful. Everything they've excelled at has leveraged the prediction or acceleration. Everything else puts them around about the same as smaller cores from Intel (Apples are huge). This is all with Intel at a process node disadvantage, and no LITTLE.big configuration. To call Atom cores a failure of Intel's ISA would be like taking only the small cores from a Qualcomm chip from 2013. ARM claims big.LITTLE can save up to 75% on power. Intel just hasn't sought to do that until now, and has only just successfully managed it. Apple originally approached Intel to design their mobile SoCs but Intel ignorantly thought it would be menial and wouldn't fit in their licensing model. To make a Watt for watt comparison isn't really possible because you're comparing the whole system not just the cores, let alone ISA let alone the implementation etc etc. If Intel brings themself to a level playing field then this is my opinion but I think there'll be little to no gap at all. RISCs lead will only be in licensing models, extensibility etc. As it currently is. This is all my opinion of course but it seems like Intel's finally had the kick in the arse they needed to stop making terrible business decisions, and x86 Will be around for a long time. None of this is excusing Intel. They don't deserve the position they're in.

You can't avoid it though. At least the way things are going they have the right idea with specialised cpus for certain tasks, graphics, AI, etc. x86 kinda tried this with the math co-cpus, then they decided to just add everything on the cpu itself. Which eventually will cause issues or slow down your cpu, or even limit you in what you can do. A specialised chip for something specific, allows you to design for this, frees you to modify your chip, instructions etc anything you need for this to achieve your goal, if you had added all to a cpu you'd be kinda limited and it will hurt you eventually. The main reason they done this is because it is initially faster - having a 2nd or a 3rd co-cpu, those will need to talk to each other, and maybe back then cpus were getting faster quicker than buses or ways to have cpus exchange info. During the years I assume they have found ways to overcome those issues, like keeping those cpus close to each other and maybe they have other tricks too to achieve super fast exchanges between cpus.

Intel tried to kill off x86 more than once, but failed. It's the software world that won't let go. Intel is kinda unwillingly stuck with x86. But I heard that Intel is gonna buy RISK-V to start manufacturing those CPUs at its own foundries. I also heard that Intel is gonna start manufacturing ARM CPUs for Qualcomm, etc. So I don't think he's trying to be neutral. What he said was, that a new clean ISA is the best. But, eventually they all become bloated. RISC-V is currently the least bloated. X86 is the oldest, and thus the most bloated. So it's not that x86 is inherently significantly worse... Its that it's bloated. If you cleaned x86 up, then it's comparison to e.g. ARM would be neutral. But, the software world would embrace such a move.

@@tylerdurden3722 You seem to believe, that intel was some kind of a good, innocent buddy or something like that. But history proofs, intel is more like a big blue shark, eating up small fishes, who might endanger intel's monopolylike power. For example intel killed transmeta and their revolutionary chips. RISC-V even poses a bigger threat to intel and therefore intel tries to buy SiFive. In Order to get rid of their competition intel even fud and bribed merchants to prefer their chips against AMD's. After that Intel got sued for that. But after the cross-licensing with AMD, intel somewhat stopped the dirty campaign against AMD, which did not stop intel to collaborate recently with their buddy Microsoft, to fit alder lake closely to Windows 11 to the disadvantage of AMD's latest CPUs. Yes intel tried to introduce a new ISA by itanium. But in truth they failed because the architecture, which has been developed with HP, was so bad. Itanium was not supposed to supersede x86. Whoever believes that, is naive towards a company like intel. The x86 patents are intel's bred and butter for decades and ensure their influential power. They are very aggressive to protect it and even gave Microsoft a warning, when the latter worked on their x86-64 emulator for Windows on Arm. Intel is very rich and got capable engineers, who try to work around the caveats of x86 to some extent. For many generations now, their CPUs aren't even pure x86 anymore. The micro architecture of intel chips are based on RISC internally, but outside they communicate over a x86 layer with programs. If intel wanted, they easily could introduce a real hybrid cpu in terms of different, mixed ISAs like for example apple's M1 to introduce a new ISA but to keep x86 as a compatibility layer for Rosetta 2. Intel only did adapt their CPUs after AMD extended the x86 by x64 extensions, which intel cross licensed. Let me finally speak about the mentioned bloat. Yes it is a problem for us pro users, developers and resources worldwide and all tech enthusiasts, who yearn for real progress and innovation. But it is not the same from the perspective of a big company like intel, which earns big money by their proprietary patent protected ISAs. As i proofed above, intel could easily introduce a new hybrid CPU with different ISAs. But why cut of a proprietary cash cow, when you still can milk it until it's death. They slow down the whole innovation process by keeping alive old patent protected technologies. When you look closely enough, you are going to notice, that intel from time to time tries to extend x86 by new proprietary extensions like MMX, SSE and AVX crap. By those, they try to establish new proprietary standards, on which programs depend. In that way, when x86-64 is going to lose patent protection after years, programs are still depend on intel's next extensions. Intel earns money by bloated chips. Real bloat-free Chips are only possible on the grounds of open and free APIs and ISAs. When those get obsolete after some years because of progress and innovation, they simply can be superseded by hybrid chips with compatibility layers. Or they even can get virtualized or temporarily wired on FPGAs etc. Hopefully my message does not get deleted by the channel again, which seems to be close with intel. Also no affront intended towards intel fans. But critique should be allowed in free and educated circles for the sake of innovation. Problems have to be addressed and not be kept under the carpet, if we want to come forward. Thanks

@@tylerdurden3722 x86 is not simply bloated. It has many instructions that were meant to be used when programming in pure assembly, combining several steps in one. Now you would focus more simpler instructions that the compiler combines as needed.

Delayed branches? Bad drugs, with branch prediction delayed branches are not needed and if ISA has them (like MIPS and SPARC), they are small annoying artifact.

Hi, I don't have your knowledge on CPU internals etc, but why do you think this is bad somehow? RISC-V has an open ISA, which you are allowed to modify and if it is true what you say, that it misses some specific fundamental instructions/components, I'm sure a manufacturer can add those if they deem this as necessary, and if they are truly fundamental, isn't this the case? Where exactly is the problem? Also, I will respectfully disagree, performance is not all that matters, even if this is the end goal for a successful cpu and arch, there are many other issues with x86 and ARM, far more important than a slight concession on performance in RISC-V. What you concede with x86 and ARM is greater than what you potentially lose with a small performance hit. And it's still early days for this arch, I'm sure it will get there.

@@giannismentz3570 The RISC-V absorbed all the best features of all the RISC processor architectures known, but not more. The RISC-V Foundation postulates: “The RISC-V ISA is based on computer architecture ideas that date back at least 40 years.” The only advantage of RISC-V is its open architecture