Note that in RISC-V there are profiles which are separate from the instruction set extensions. You can have an application profile for running Linux and a different microcontroller profile for embedded applications. Each profile specifies a base instruction set and a set of mandatory extensions plus some non ISA details (like the interrupt controller and debug mechanism). A system can implement a profile but also add extensions that the profile doesn't mandate. If such an optional extension proves to be popular enough, it might become mandatory in a future version of that profile. But these instructions will remain an extension - they will never get added to the base ISA. This allows one profile to get more bloated without necessarily affecting other profiles.

Super informative. Thanks for breaking this all down in an approachable way

Great great video, exactly the type content I was looking for. Thank you so much for sharing your insights

Thanks for the very informative video. Very insightful

Well, this CISC and x86... The CISC architecture could be thought of several special purpose RISC subunits to decide and execute the instructions. Lots of the x86 implementations have RISC CPUs in them to do management and microcode stuff.

Thanks for the explanation👍

As always straight to the point and with solid facts.

Great video, thanks for such a straightforward breakdown.

Thanks for producing these fine videos. For folks interested in more details about RISC-V, I recommend the book "The RISC-V READER" by Patterson and Waterman.

Thanks DJ👍

Nice. Thanks DJ

Thanks 😁

I have always considered the Control Date 6000 series to be the fist serious RISC architecture. A bit of Seymour Cray brilliance.

In the early MIPS days the pipeline was very visible to the programmer. Accessing some result too early wouldn't work (a pipeline hazard) rather than wait for it (a pipeline stall). Of course you'd want to avoid stalls too and the assembler even reorganized instructions for you unless you told it not to (for example by putting instructions in the branch delay slot).

Thanks DJ, highly interesting as always. Reminds me of the Acorn Archimedes, which I almost bought who knows back when, just for the heck of RISC. Anyway, new sub here: What is the best way of humbly proposing topics for future videos?

There is also a tradeoff in silicon. The logic needed to perform each complex instruction must exist on the wafer even when this instruction is not needed. The remaining functionality then must work around this area within the speed of light limit and the capacitance of the longer traces. One or two of these functions might use as much silicon as an entire RISC core. Each complex instruction can perform that function faster and more efficiently than any other implementation; but few programs use every complex instruction and some programs use none.

The difference between RISC and CISC has become blurry, but one difference which still stands is the split between memory access and arithmetic. In a RISC processor, an instruction can access memory, can perform arithmetic operations but can NOT do both (e.g. 'inc ', found even on the MOS 6502). Also, both ARM and RISC-V have fixed-sized instructions, even though it's not a RISC requirement.

It was my understanding that the extra power consumption of *modern x86* is mainly found in the instruction decode module, the speculative execution, and related out-of-order pipeline support circuits rather than strictly in the logic processesing core. In the core the execution of an operation is effectively the same set of internal register moves and clock cycles regarding a basic integer calculation. (Setting aside special modules, coprocessors, and such. Most ARM don't even have float module.) Further complication is microcode that converts an external CISC instruction into internal RISC instructions; and on the other team certain combinations of simple external RISC instructions can be fused to make a more complex internal instruction.(saving an instruction register load and maybe a clockcycle or two) Then externally we see maybe 16-32 registers, yet hardware may have well over 200. There was also a time long ago when CISC was being forcast to evolve into a hardware high level language interpreter, sort of like a Python ASIC. In any case I have seen some analysis that show for small embedded stuff that isn't dominated by caches and pipelines, RISC-V can be implemented in less physical area than ARM which is direct cost savings as raw chip manufacturing cost rises with the square of chip area.(Of course the package cost dilutes the advantage a bit, but many are used as blob on board without solderable packages.)

In terms of energy consumption, I see two ways RISC processors have an edge over CISC: - Intel processors split their instructions into micro-instructions, whereas I'm not aware ARM processors do. If that's the case, it means extra transistors for Intel CPUs, which means more heat generation - Fixed-length instructions are easier to handle, allowing a simpler design. You won't gain in performance but will cut down on extra transistors to deal with variable-length instructions I do not know to what extent those factors matter, but it is also true that the one thing we've asked Intel/AMD is 1) more powerful processors and 2) backward compatibility, so energy consumption was never the top priority. ARM, on the other hand, had energy consumption pressure starting with their very first version (even though it was designed for a desktop computer)

Excellent video thank you. IMHO one of the reasons RISC-V is attractive is because a nation state can't embargo it.

CISC instructions are more complex and take more cycles to execute. Due to multiple execution paths. CISC architectures have variable length instructions. Multiple argument combinations affect how an instruction is read and how it is executed. RISC has a well-defined fixed-length instructions that take certain clock cycles to execute. The emphasis in CISC is on smarts in the hardware, while RISC is optimized through the instructions that it get - the software that you as a developer write. Yet CISC CPUs are nowadays implemented with RISC concepts under the hood. So a complex instruction might be unfolded into multiple instructions that also can be reordered and optimized so to reduce clock cycles.

ARM is making moves into the server space. As of today the Fugaku supercomputer is the 2nd most powerful super computer in the world and it is based on ARM CPUs. Companies copy Apple and they are seeing the power of ARM based Macs. Rumors state Microsft is working on a custom CPU for their Surface line. It will be interesting to see the performance of the new Mac Pros based on ARM.

Thanks for the video ! Very informative. Regarding CISC vs RISC, in the early days, most commercial ISAs were CISC. Like 6504, 68000 etc, these were the days when people were still writing assembly. In time, as compilers and higher level languages emerged, it made more sense to take away the complexity from ISA and put it into compilers. By doing this, they were able to make CPU cores smaller, efficient and robust. (Thats the story I heard in the uni anyway lol :) ) I have another question though, how different is Apple Silicon to ARM ? I think they have some extensions ? Does Apple pay fees to ARM ? Also, does Apple have any plans to go into the server market ? It's not their effigy, but I think there is a great potential for them there. Apple silicon is very efficient and powerful. Also, community is building the software for them, you can run linux on M1.

is it true risc-v is more integer based and amd64 is focused on floating point? to me integer based to me means microcontroller applications dealing with timers and bools/bytes, and floating point means cartesian-coordinates/math based applications.... not sure though

👍👍

I think you forgot to mention the third processor type. I'm assuming you were referring to Very Long Instruction Word (VLIW) design? Those never quite panned out like we hoped. I doubt anyone even remembers Transmeta's attempts to make the design mainstream.

Plot twist, Intel is already RISC. In fact the native opcodes of the Intel CPU's are similar to ARM. The x86 instruction set is being emulated in software(microcode) inside the CPU. Most likely this happened when Intel acquired Transmeta's patents. Transmeta was a CPU company that emulated assembly instructions sets inside the CPU which they called "Code Morphing Software". So for those of you who did not get the memo.... RISC won, and CISC died a long time ago.

AWS is pushing their ARM based cpu graviton on their cloud and it's cheaper with the same performance as x86 architectures. They acquired some ARM special company to build these cpus specially for the cloud.

What about DSP and SDR embedded environments

The law suit between ARM and Qualcomm over the licensing agreements after the acquisition of Nuvia has given RISC V increased popularity. Nuvia are promising to do similar to what Apple did with their M Series Silicon by offering desktop performance with mobile efficiency. It would be amazing to have an architecture from RISC V that can scale from iot, euv, smartphone, tablet, laptop, desktop, edge, server. I now use a smartphone for majority of my needs. I’m used to the screen size and the limited multitasking, switching to a foldable or dual only increases my productivity. One day my smartphone will be able to run a full desktop pro app and play games natively at 4k 120Hz with raytracing. I’ll probably never need to upgrade it.

What are your thoughts about VLIW?

18:08 The x86 ISA has without a doubt evolved since 1978. HPC and machine learning systems that only need 24GB/CPU are probably salivating over the Apple M2 chip; too bad they can't build servers with them...

Will run Debian RISC V in Qemu and check it out.

ARM just pulled an AT&T by suing Qualcomm for the Nuvia CPU. The 8cx can't compete with Apple silicon and the Qualcomm's Nuvia CPU could have changed that.

could you please use slides during the talk? it would be easier to follow the technical talks

How about a factory building user designed chip. Ie , personal DESIGNED CPU / GPU. PC.

The distinction between RISC and CISC "philosophy" is more and more blurred. Almost all CICS processors are microcoded and deeply pipelined, often achieving superscalar performance. One could say that RISC processors put the burden of optimizations like branch prediction and instruction reordering on the compiler, while CISCs do that themselves. In theory, the compiler has more information on the program structure and should be better at those optimizations.

I saw Debian 11 has a RISC V ISO. Should Programmers start supporting RISC V?

18:40 The #2 supercomputer in the world is ARM right now

Forgot about compressed instructions in RiscV. Anything open source will dominate market and win

Here is Jim Keller's take on the subject. He has worked and Intel and AMD. He's the chief architect for Ryzen. ukposts.info/have/v-deo/sYR-hn18iZCjsnk.html I find his take on important instructions and variable length instructions fascinating. It leads me to think of an instruction set like Unicode, something like RISC and VLIW in one ISA.

my cellphone has a more powerfull cpu then my first servers i setup,and it can run on battery for a full day and fits in my pocket,i think power usage will at some point become a problem for both amd and intel,apples m1 and m2 is doing really well its a shame its locked in to apples realm.

second!!

*You forgot to link to a video on security extensions. Instead there's a link to Home Lab video.* This video started completely beginner-friendly, then suddenly escalated to some wacky expert knowledge stuff about virtualization, "MMUs". Then hovered somewhere in the middle because of terms like "IOT" and "edge" thrown in (IOT is a widely-known one, but few people would remember it by acronym, because its hype train passed long time ago with no tangible success).

RISC v is very cool, but the formal Isa guidelines are extremely complicated to follow lol, there are very many levels and it’s really cool, but Jesus is it hard to explain to someone without domain knowledge

Entropy guarantees a hybrid clusterfuck of a hack.

Nope, RISC-V is open standard ISA not Open Source License !!!

Now that China is adopting RiscV wholesale, Intel, Amd, and Arm are dead.

RISC-V has higher hip value. Which effectively proves nothing at all.

in short answer. risc will be winner..

Good luck offering a "RISC-V" processor, without an annual subscription to the alliance and paying to have your implementation CERTIFIED. Let alone purchasing licences for the 90% of the die that incorporate proprietary, standards essential buses, memory controllers, ...

Armv8 is barely RISC anymore...

The RISC-V does not contain innovative ideas in microprocessor design capable of replacing existing processors such as x86 and ARM. The RISC-V processor is not suitable as a candidate for this role. They say “RISC-V does not represent new technology”. The RISC-V has no novelty potential. The tomorrow’s world needs completely new architectural ideas as familiar processors x86 and ARM are morally obsolete architecturally. I propose the novel architectural idea, see my article, address is below in this comment. The RISC-V is good for embedded systems, controllers, and similar as free and open. There are other positives and improvements, but they are on the engineering level. But the RISC-V will never become a general all-purpose processor. The RISC-V is based on 40-year old ideas as RISC-V Foundation claims. There is no sense to port the huge x86 and ARM software ecosystems on it. Thus, RISC-V will never gain a victory over x86 and ARM. The most of positives about the RISC-V processor are arbitrary speculations. Actually, the main advantage/benefit of RISC-V is free and open architecture (open ISA). The RISC-V processor has instructions with variable lengths, consisting of 2-byte snippets. It is strange, it is bad being a deviation from the classic, absolute, and pure RISC principles well formulated at the beginning of the RISC era. Also the RISC-V processor has 6 instruction formats, and it is too many. I sceptically evaluate the RISC-V microprocessor, because it is based on old ideas and does not advance computer science and practice, freezing the long-achieved scientific and technical levels. However, I pay tribute to the creators of the ideas of the RISC microprocessor, with the main feature to perform all arithmetic/logical operations only on registers, and use external RAM only to load/store processed data. I also pay tribute to the idea of the free and open computer architecture (not patented instruction set architecture). The Contemporary microprocessors contain 8 specific hardware components: (1) SMT (Simultaneous Multithreading), (2) register renaming, (3) instruction reordering, (4) out-of-order execution, (5) speculative execution, (6) superscalar execution, (7) delayed branch, (8) branch prediction. These components make up some kind of a “magnificent eight” of components which essentially raise the performance of microprocessors. But unfortunately they are very complex. A processor core having these components is a full-fledged one, otherwise it is good for simple applications, e. g. for embedded systems, controllers etc. The “magnificent eight” of components is very hard to design, only the experienced firms and developers are able to do this, and much know-how was acquired, some effective solutions are patented. Particularly complex is the SMT. Only powerful and advanced firms like Intel, AMD, IBM are able to equip their processors with the “magnificent eight” components. It is not surprising that some Intel processors, and the famous Apple's M1 processor do not contain SMTs. If a company is able create the full-fledged RISC-V processor with all “magnificent eight” components then it would be a serious achievement, and such RISC-V would be considered of the World's class comparable with x86, with ARM, but not more. As far as I understand most of the developed RISC-V processors have no components from the “magnificent eight”, and are intended for embedded systems. A course directed on further development of RISC-V is a wrong way, and leads the computer architecture to deadlock. The RISC-V is not promising for computer industry. In fact, RISC-V hampers the further development of the state-of-the-art microprocessor technologies. The World demands absolutely novel microprocessor having much more higher performance than all contemporary ones. The novel and effective ideas on computer architectures do exist! Here’s such a novel processor architecture in article V. K. Dobrovolskyi. “Microprocessor Based on the Minimal Hardware Principle”. The article is published in scientific magazine Electronic Modeling (Електронне моделювання), 2019, vol 41, No 6. pp. 77-90. The magazine is posted in the Internet: www.emodel.org.ua/en/ touch ARCHIVE, move to 2019, then to VOL 41, NO 6, (2019) then click Microprocessor Based on the Minimal Hardware Principle, then go below to Full text: PDF, and click PDF. My novel processor architecture does not have the “magnificent eight”, The “eight” is not necessary at all. This comment reflects different view on the RISC-V architecture, and the computer community has a right to become familiar with such a view. I’m Volodymyr Dobrovolskyi (V.K.Dobrovolskyi).

Very disappointing that the discussion quickly turned in cisc vs risc. As one can see macs turned to RISK which appears to be more efficient for laptops than current cisc and for servers amazon EC2 runs ARM machine types which have better performance to price ratio for many workloads than amd64. So as a whole this video seems to be a waste of time.