Oh, that's a while back. I have a couple of ideas on how to improve this now but I'll see if I can dig this stuff out.

@@weirdboyjim no stress, if you are not able to find it, no problem!

Indeed, macros have been on the "todo list" for a while, but as I'm sure you can imagine my backlog of things that would be handy is pretty large. It's difficult to prioritize sometimes.

I ordered a SDS1202X-E today. It will be infinitely better than not having one at all I think.

From my experience I've need hit anything where the speed as been a concern. I have hit a couple of places where extra channels would have been handy, working out how to use the external trigger alleviates that a bit.

You mean the microscope? ukposts.info/have/v-deo/bn5zhXmnen6lrIU.htmlsi=4cjRrJ1_Mk0ca4qW

Glad you are enjoying it!

Very generous! I’m in Rome for a few days so it may have to be Gelato! The spi is definitely moving towards storage, I occasionally just let it run slowly to watch the led’s!

This is a discussion that almost needs a video on it's own. Memory Mapped IO (I do a little of this in the vga circuit) is really just IO implemented as memory operations without additional support from the cpu. Processors like the z80 have dedicated IO circuitry which still works very much like memory but separates the address space out. But those two are not the only way to do it, the "IO Ports" on my build work more like some microcomputers. The bus is the internal main bus and those "port's" are just otherwise unused addresses for main bus devices, reading or writing to a port is exactly the same as asserting or loading one of the 8-bit registers. There is no hardware at all to support the IO in the core cpu, the only things it costs me is the instruction space. In this particular architecture the IO is indeed faster since it never touches the memory system so it doesn't cause a fetch stall.

It's always a balance on circuit verses code complexity. My tightest loop here is 3 cycles of action verses 5 cycles of delay, so I would only gain 5 cycles of parallelism for each byte of fifo (minus any management code). My sense is that I'm probably at the sweet spot for this build, but it's easy to see how that balance can shift rapidly.

Good to hear you are enjoying it!

Someones paying attention! 😉

A compiler would be an interesting thing to have, but code generation for 8-bit architectures tends to be pretty inefficient. I'm expecting future builds to achieve more in this regard.

Nice idea, but that would overlap with the vga project.

It started out as a few bits of common circuit I used on a breadboard. It has a d-type latch, a couple of line drivers and some debounced buttons. I was using that a lot of test bits of the circuit. I converted it to pcb for reliability. ukposts.info/have/v-deo/maKmaG5pfZyJzZ8.html

Glad I didn't disappoint (this time).

@@weirdboyjim Never known you disappoint, provide talking points yes but disappoint no. 🙂

Thanks TwoBob!

Dma would require support on the cpu side that I don’t have, you may need to wait for the next cpu build for that.

@@weirdboyjim something simmilar would still be posible, as it's own devices with it's own memory. Essentially an autonomous buffer which could opperate at different speeds from the cpu and would remove the nops with a flag check. But this only makes sense when you plan on adding multi-theading.

Good to hear you are enjoying!

Thanks!

Interrupts rarely work with low enough latency, you would want some buffering as well.

Very kind of you to say that!

😊 thank you

Hope it doesn’t disappoint!

Lots of interesting things once I have storage!

Thanks Lol, Glad you are enjoying anyway.

Thank you very much!

Thanks for watching!

That is good to hear! In many regards assembly language is really easy to follow once you have a rough idea of what the instructions do (and good naming helps with that!).

Ha! I expect you probably do. What you don't know is the first big demo that's going to use it! 😉

@@weirdboyjim Well, removing bit banging serial did evoke some memories. And I know one thing that use spi almost exclusively. Ohhh, demos are always fun, all parts of them. 😉

Thanks! Glad you liked it!

The ability of SD cards to talk SPI is indeed an interesting possibility...

Remember the first few iterations of the MIPS architecture had a branch delay slot that was invariably filled with a NOP by the compiler, let alone the programmer 😂 What you have will no doubt work for you, but possibly it's worth an auto clock counter so that you can trigger it and it just pumps the 8 bits. Could be triggered by the control line that currently controls the mux. Then you can overlap writing the Rx data to ram while the next byte is being clocked in, without having to be 100% cycle count accurate in the 'filler' code. Only worth it if the equivalent of *pointer++ = register takes more than 5 cycles or is nondeterministic.

Far more common at the low level than many people realize!

You can indeed do it with just one shift register, but you need one of the more complex parts that can handle parallel read and write. The circuit logic is not any simpler and I felt it was easier to explain the separate functionality by handling shift in/out separately.

@@weirdboyjim 🤔so that's why 299 wasn't used

SD Card, I couldn't possible comment 😅. I'm not 100% sure about bankable ram, while it would be nice to have more memory none of my plans really need it. I'd rather save a larger memory pool for a future architecture that's designed to be able to make use of it.

A couple of reasons, but my reasons are not necessarily great. My preference was to use commonly available parts that are also available in a wide variety of logic types. 869 seems to be a less common Part that only comes in a limited range of families. In terms of your own circuit design there is definitely scope to use them though.

Yeah, I wasn't expecting anyone to try and do this, so I'm mostly just doing whatever is easiest for me at the time.

@@weirdboyjim Which does makes sense tbh. I know it's much easier to be an armchair critic than a content creator so thank you for what you do!

I think it's all going to fit ok, working inside the constraints is an extra bit of challenge I like having. If I was really tight I could always stick a few passives on the back but I'd rather not do that. I appreciate my self imposed design constraints are not for everyone. The nearest I came to risers was for the Audio circuit, I thought I could stack channels above one another if I needed to without loosing much.

Sorry, I only speak English. I tried google translate but it didn't seem right.

I really kicked myself over that one. I am debating how I show the mistakes in videos, perhaps I should highlight them explicitly when I make them?

@@weirdboyjim I like the chillaxing pace without breaks and blips. You are explaining your mistakes quite well without relying on highlights. And I find more amusing to spot those from my backseat when I do it without help... 😄

Those are printed with a "Dynamo Letratag", really useful little thing. I label lots of my storage boxes, chips etc.. with it.

@@weirdboyjim Nice, I ended up just using sticky paper and my regular printer, I figure it works fine too. Less spending! I like when I figure out cheaper solutions like this.

Glad you enjoyed!

Glad you enjoyed it!

Thanks!